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TM5400/TM5600 Data Book
November 1, 2000
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November 1, 2000
TM5400/TM5600 Data Book
CrusoeTM Processor Model TM5400/TM5600
Data Book TMDFA-13 Revision 1.3 Confidential Information--NDA Required Revision History: 1.0 1.1 1.2 1.3 Initial release. (2/18/00) Added TM5600. Changed frequency/voltage SKUs. Corrected sequential pin listing and added alphabetic pin listing. Removed S_CLK[7:4]. Updated electrical specs. (5/25/00) Added SDR/DDR interface memory timing tables, thermal diode specs, new package drawings, updated package marking specifications. (10/23/00) Removed 633 MHz SKU (11/1/00)
Property of: Transmeta Corporation 3940 Freedom Circle Santa Clara, CA 95054 USA (408) 919-3000 http://www.transmeta.com The information contained in this document is provided solely for use in connection with Transmeta products, and Transmeta reserves all rights in and to such information and the products discussed herein. This document should not be construed as transferring or granting a license to any intellectual property rights, whether express, implied, arising through estoppel or otherwise. Except as may be agreed in writing by Transmeta, all Transmeta products are provided "as is" and without a warranty of any kind, and Transmeta hereby disclaims all warranties, express or implied, relating to Transmeta's products, including, but not limited to, the implied warranties of merchantability, fitness for a particular purpose and noninfringement of third party intellectual property. Transmeta products may contain design defects or errors which may cause the products to deviate from published specifications, and Transmeta documents may contain inaccurate information. Transmeta makes no representations or warranties with respect to the accuracy or completeness of the information contained in this document, and Transmeta reserves the right to change product descriptions and product specifications at any time, without notice. Transmeta products have not been designed, tested, or manufactured for use in any application where failure, malfunction, or inaccuracy carries a risk of death, bodily injury, or damage to tangible property, including, but not limited to, use in factory control systems, medical devices or facilities, nuclear facilities, aircraft, watercraft or automobile navigation or communication, emergency systems, or other applications with a similar degree of potential hazard. Transmeta reserves the right to discontinue any product or product document at any time without notice, or to change any feature or function of any Transmeta product or product document at any time without notice. Trademarks: Transmeta, the Transmeta logo, Crusoe, the Crusoe logo, Code Morphing, and combinations thereof are trademarks of Transmeta Corporation in the USA and other countries. Other product names and brands used in this document are for identification purposes only, and are the property of their respective owners. Copyright (c) 1999-2000 Transmeta Corporation. All rights reserved.
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Table of Contents
Introduction ................................................................................................................... 9 Chapter 1 Functional Interface Description ........................................................................... 13 1.1 1.2 1.3 DDR SDRAM Interface .................................................................13 SDR SDRAM Interface..................................................................14 PCI Interface..................................................................................16
1.3.1 1.3.2 PCI Bus Commands .................................................................................... 16 Bus Arbitration ........................................................................................... 17
1.4 1.5 1.6 1.7
Southbridge Sidebands..................................................................19 Serial Interfaces ............................................................................19 Clocks .............................................................................................20 Power Management.......................................................................21
1.7.1 1.7.2 Power Management States ......................................................................... 21 SDRAM Power Saving Mode ...................................................................... 23
1.8 1.9 1.10 Chapter 2
Test and Debug..............................................................................24 Supply Voltages .............................................................................24 Power On Sequence .......................................................................25
Pin Description ........................................................................................................... 27 2.1 2.2 2.3 Signal Definitions ..........................................................................27 I/O Signal Listings.........................................................................38 Footprint and Pin Assignments ....................................................40
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Chapter 3
Electrical Specifications ...........................................................................................53 3.1 3.2 3.3 3.4 3.5 Absolute Maximum Ratings ......................................................... 53 Recommended Operating Conditions .......................................... 54 Power and Current Specifications ............................................... 55 DC Specifications for I/O Signals ................................................. 57 Timing Specifications for I/O Signals .......................................... 59
3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.5.8 3.5.9 General AC Testing Conditions ..................................................................59 Power On Specifications ..............................................................................60 Input Clocks .................................................................................................62 DDR SDRAM Interface ...............................................................................64 SDR SDRAM Interface ................................................................................69 PCI Interface................................................................................................74 Southbridge Sidebands and Power Management Interface ......................74 Debug Interface ...........................................................................................75 Code Morphing Software Boot ROM Interface ..........................................76
3.5.10 Configuration ROM Interface .....................................................................77 3.5.11 JTAG Interface ............................................................................................78
Chapter 4
Mechanical Specifications .......................................................................................81 4.1 Thermal Specifications ................................................................. 81
4.1.1 Thermal Diode .............................................................................................81
4.2 4.3
Package Dimensions ..................................................................... 82 Package Marking .......................................................................... 85
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List of Tables
TABLE 1 ..................................................DDR SDRAM Memory Configurations 13 TABLE 2 ................ Core and DDR SDRAM Interface Frequency Configurations 14 TABLE 3 ...................................................SDR SDRAM Memory Configurations 15 TABLE 4 .........................Core and SDR SDRAM Bus Frequency Configurations 15 TABLE 5 ............................................................... PCI Bus Commands Supported 17 TABLE 6 .......................................................... Power Management System States 21 TABLE 7 .........................................TM5400/TM5600 Power Management States 22 TABLE 8 .......................................................................................Signal Summary 27 TABLE 9 ..............................................................DDR SDRAM Interface Signals 28 TABLE 10 Logical Alignment of DDR Byte Enables, Data Strobes and Data Bits 29 TABLE 11............................................................. SDR SDRAM Interface Signals 30 TABLE 12 ..Logical Alignment of SDR Clocks, Clock Enables, and Chip Selects 31 TABLE 13 ....................... Logical Alignment of SDR Byte Enables and Data Bits 31 TABLE 14 ...............................................................Memory Address Translations 32 TABLE 15 ............................................................................. PCI Interface Signals 33 TABLE 16 ................................................ Southbridge Sideband Interface Signals 34 TABLE 17 .......................................................................... Serial Interface Signals 34 TABLE 18 ............................................................ Master Clock and Reset Signals 35 TABLE 19 ................................................... Power Management Interface Signals 35 TABLE 20 ........................................................................... Miscellaneous Signals 36 TABLE 21 .......................................................................... JTAG Interface Signals 37 TABLE 22 .................................................................... Power and Ground Signals 37 TABLE 23 ................................................................................. Input Only Signals 38
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TABLE 24............................................................................... Output Only Signals 39 TABLE 25...............................................................................Bidirectional Signals 40 TABLE 26................TM5400/TM5600 Pin Assignments - Sorted by Pin Number 42 TABLE 27............. TM5400/TM5600 Pin Assignments - Sorted by Signal Name) 47 TABLE 28...................................................................Absolute Maximum Ratings 53 TABLE 29.....................................................Recommended Operating Conditions 54 TABLE 30................................................ TM5400/TM5600 Power Specifications 55 TABLE 31..................................... TM5400/TM5600 Peak Current Specifications 56 TABLE 32.... DC Specs for All Signals Except PCI and DDR SDRAM Interfaces 57 TABLE 33..................................... DC Specifications for DDR SDRAM Interface 57 TABLE 34.......................................................DC Specifications for PCI Interface 58 TABLE 35................................................................ Thermal Diode Specifications 58 TABLE 36..............................................................General AC Testing Conditions 59 TABLE 37........................................................................ Power On Specifications 60 TABLE 38..................................................Timing Specifications for Input Clocks 62 TABLE 39............................... Timing Specifications for DDR SDRAM Interface 64 TABLE 40.......tohold and tvalid Timing Specifications for DDR SDRAM Interface 66 TABLE 41................................ Timing Specifications for SDR SDRAM Interface 69 TABLE 42....... tohold and tvalid Timing Specifications for SDR SDRAM Interface 71 TABLE 43.................................................Timing Specifications for PCI Interface 74 TABLE 44............................................ Timing Specifications for Debug Interface 75 TABLE 45.Code Morphing Software Boot ROM Interface Timing Specifications 76 TABLE 46...................... Timing Specifications for Configuration ROM Interface 77 TABLE 47..............................................Timing Specifications for JTAG Interface 78 TABLE 48...............................................................Package Marking Descriptions 86
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List of Figures
FIGURE 1..........................................................TM5400/TM5600 Block Diagram 11 FIGURE 2............................................................ PCI Arbitration Priority Scheme 18 FIGURE 3........................................................ Power Management State Machine 23 FIGURE 4..................................................... Package Footprint - Top Down View 41 FIGURE 5..................................... General AC Test and Measurement Conditions 59 FIGURE 6....................................................................................Power On Timing 61 FIGURE 7..................................................Timing Specifications for Input Clocks 63 FIGURE 8..........Timing Specifications for DDR SDRAM Interface - Read Cycle 67 FIGURE 9.........Timing Specifications for DDR SDRAM Interface - Write Cycle 68 FIGURE 10....... SDR SDRAM Input Setup/Hold and Output Delay/Hold Timing 70 FIGURE 11........ Timing Specifications for SDR SDRAM Interface - Read Cycle 72 FIGURE 12....... Timing Specifications for SDR SDRAM Interface - Write Cycle 73 FIGURE 13...........................................Timing Specifications for Debug Interface 75 FIGURE 14Code Morphing Software Boot ROM Interface Timing Specifications 76 FIGURE 15.....................Timing Specifications for Configuration ROM Interface 77 FIGURE 16............................................Timing Specifications for JTAG Interface 79 FIGURE 17.............................................. Package Marking Locations - Top View 85
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Introduction
The Transmeta CrusoeTM Processor Model TM5400/TM5600 is a high performance, low power microprocessor based on a VLIW core architecture. When combined with Transmeta's x86 Code MorphingTM software, the TM5400/TM5600 provides x86compatible code execution. The TM5400/TM5600 delivers a highly integrated, costeffective solution by incorporating an L2 cache, support for single data rate (SDR) and double data rate (DDR) SDRAM, and a PCI controller. Additionally, the TM5400/TM5600 provides power management controls, SMM and thermal monitoring capability, and operates from a low voltage supply (1.2-1.6 V), making it ideal for mobile applications.
CrusoeTM Processor Model TM5400/TM5600 Feature Set
* * * * VLIW processor and x86 Code Morphing software provides x86-compatible mobile platform solution 500, 533, 600, and 667 MHz operating frequencies Integrated 64 kByte L1 instruction and data caches, and 256 kByte (TM5400) or 512 kByte (TM5600) L2 write-back cache Integrated northbridge core logic features facilitate compact system designs * * * * DDR SDRAM memory controller with 100-133 MHz, 2.5V interface SDR SDRAM memory controller with 66-133 MHz, 3.3V interface PCI bus controller (PCI 2.1 compliant) with 33 MHz, 3.3V interface
LongRunTM advanced power management with ultra-low power operation extends battery life * * 0.7-2.5 W @ 500-667 MHz, 1.2-1.6V running typical multimedia applications 100 mW in deep sleep
* * *
Power management controls for ACPI-compliant modes Full System Management Mode (SMM) support Compact 474-pin ceramic BGA package
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The processor core operates from a 1.2-1.6 V supply, resulting in extremely low power consumption even at high operating frequencies. The processor typically consumes only 0.7-2.5 Watts under normal operating conditions. When operating in deep sleep, power consumption drops below 100 mW.
Architectural Overview
The Transmeta Crusoe Processor model TM5400/TM5600 is an ultra-low power, highspeed microprocessor based on an advanced VLIW core architecture. When used in conjunction with Transmeta's x86 Code Morphing software, the TM5400/TM5600 provides x86-compatible software execution using dynamic binary code translation, without requiring code recompilation. In addition to the VLIW core, the processor incorporates separate 64 kByte L1 instruction and data caches, a large L2 write-back cache (256 kByte on TM5400, 512 kByte on TM5600), a 64-bit DDR SDRAM memory controller, a 64-bit SDR SDRAM memory controller, and a 32-bit PCI controller. These additional functional units, which are typically part of the core system logic that surrounds the microprocessor, allow the TM5400/TM5600 to provide a highly integrated, cost-effective platform solution for the x86 mobile market. The TM5400/TM5600 processor core is relatively simple by current standards. It is based on a Very Long Instruction Word (VLIW) instruction set of 64 or 128 bits. By utilizing a VLIW architecture, the control logic of the TM5400/TM5600 is kept simple since software controls the scheduling of TM5400/TM5600 instructions. This leaves the hardware with an in-order 7-stage integer pipeline and a 10-stage floating point pipeline. By streamlining the hardware, performance can be improved over traditional x86 architectures by increasing the operating frequency. Other than having the hardware execute arithmetic, shift, and floating point instructions similarly to an x86 processor, the TM5400/TM5600 does not have the same features as a traditional x86 design. To ease the translation process from x86 to TM5400/TM5600 code, the hardware generates the same condition codes as an x86 and it operates on the same 80-bit floating point numbers. Also, the TM5400/TM5600 Translation Look-aside Buffer (TLB) has the same protection bits and address mapping as an x86. It is up to the software to emulate all other features of the x86 architecture. The software that is tasked with converting the x86 programs into TM5400/TM5600 programs is called Code Morphing software. The combination of Code Morphing software and the TM5400/ TM5600 hardware device together act as an x86-compatible microprocessor.
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Block Diagram
The TM5400/TM5600 block diagram is shown in the following figure: FIGURE 1
TM5400/TM5600 Block Diagram
L1 Instruction Cache
64 kBytes 8-way set associative
Unified TLB
256 entries 4-way set associative
DDR SDRAM Controller
64
Processor Core
Integer unit Floating point unit MMU Multimedia Instructions
Bus Interface
SDR SDRAM Controller
64
L1 Data Cache
64 kBytes 16-way set associative
L2 Write-back Cache
256/512 kBytes 4-way set associative DMA
PCI Controller & Southbridge Interface
TM5400/TM5600
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Reference Documents
The following documents should be used in conjunction with this specification:
TM5400/TM5600 Package Specifications and Manufacturing Guide TM5400/TM5600 System Design Guide TM5400/TM5600 Thermal Design Guide TM5400/TM5600 Development and Manufacturing Guide TM5400/TM5600 BSDL Test Files TM5400/TM5600 IBIS Models TM5400/TM5600/Code Morphing Software Version 4.1 BIOS Programmer's Guide TM5400/TM5600/Code Morphing Software Version 4.1.x Release Notes TM5400/TM5600/Code Morphing Software Version 4.1.x Errata PCI Local Bus Specification
Transmeta TMDFP-xx
Transmeta TMDFS-xx Transmeta TMDFT-xx Transmeta TMDFD-xx
Transmeta TMDFB-xx
PCI SIG Revision 2.1
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Chapter 1
Functional Interface Description
1.1 DDR SDRAM Interface
The DDR SDRAM interface is the highest performance memory interface available on the TM5400/TM5600. The DDR SDRAM controller supports only double data rate (DDR) SDRAM and transfers data at a rate that is twice the clock frequency of the interface. The DDR SDRAM controller supports the equivalent of two DIMMs (up to four rows) of double data rate (DDR) SDRAM using a 64-bit wide interface. The DDR SDRAM can be populated with 64-Mbit, 128-Mbit, or 256-Mbit devices. For the highest performance, it is recommended that the DDR SDRAM devices be soldered to the planar rather than incorporated on DIMMs. Also, to reduce signal loading, only x8, x16 or x32 devices should be used. Table 1 shows possible DDR SDRAM configurations for a TM5400/TM5600-based system.
TABLE 1
DDR SDRAM Memory Configurations
DDR Device Size (Mbits)
64
DDR Device Configuration
2M x 32 4M x 16 8M x 8
Number of Devices per Row
2 4 8 2 4 8 2 4 8
Memory Size per Row (MBytes)
16 32 64 32 64 128 64 128 256
Maximum Rows
4 4 4 4 4 4 4 4 4
Maximum Memory Size (MBytes)
64 128 256 128 256 512 256 512 1024
128
4M x 32 8M x 16 16M x 8
256
8M x 32 16M x 16 32M x 8
The frequency setting for the DDR SDRAM interface is initialized during the boot sequence from data stored in the configuration ROM. Although the TM5400/TM5600 can be configured for a DDR interface frequency in the range of 1/2 to 1/15 of the core frequency, the supported interface frequency is between 100 and 133 MHz as shown in Table 2.
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TABLE 2
Core and DDR SDRAM Interface Frequency Configurations
Core Frequency
667 MHz 600 MHz 533 MHz 500 MHz
DDR Interface Frequency Divider
5 5 4 4
DDR Interface Frequency
133 MHz 120 MHz 133 MHz 125 MHz
DDR Data Rate
267 MHz 240 MHz 267 MHz 250 MHz
With LongRun enabled, the core frequency is lowered during times when peak performance is not required. When the core frequency changes, the DDR SDRAM interface frequency is recalculated to match the new core frequency setting. For example, a 600 MHz device with a 120 MHz memory interface may have a LongRun setting of 533 MHz with a 133 MHz memory interface. Therefore, TM5400/TM5600-based systems that use LongRun must support the entire DDR SDRAM interface frequency range of 100 to 133 MHz.
1.2 SDR SDRAM Interface
The SDR SDRAM controller supports up to two DIMMS (up to four rows) of single data rate (SDR) SDRAM that can be configured as 64-bit or 72-bit DIMMs. These DIMMs can be populated with 64-Mbit, 128-Mbit or 256-Mbit devices. All DIMMs must use the same frequency SDRAMs but there are no restrictions on mixing different DIMM configurations into each DIMM slot. Table 3 shows possible SDR SDRAM configurations for a TM5400/TM5600-based system. The maximum memory size in Table 3 assumes two double-sided DIMMs of identical configuration and a maximum of 16 total devices per DIMM.
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TABLE 3
SDR SDRAM Memory Configurations
SDR Device Size (Mbits)
64
SDR Device Configuration
4M x 16 8M x 8 16M x 4
Number of Devices per Row
4 8 16 2 4 8 16 2 4 8 16
Memory Size per Row (MBytes)
32 64 128 32 64 128 256 64 128 256 512
Maximum Rows
4 4 2 4 4 4 2 4 4 4 2
Maximum Memory Size (MBytes)
128 256 256 128 256 512 512 256 512 1024 1024
128
4M x 32 8M x 16 16M x 8 32M x 4
256
8M x 32 16M x 16 32M x 8 64M x 4
The frequency setting for the SDR SDRAM interface is initialized during the boot sequence from data stored in the configuration ROM. Although the TM5400/TM5600 can be configured for an SDR interface frequency in the range of 1/2 to 1/15 of the core frequency, the supported interface frequency is between 66 and 133 MHz as shown in Table 4. It is also recommended that a maximum of 8 devices per DIMM be used in order to operate at the listed frequencies with the proper signal integrity.
TABLE 4
Core and SDR SDRAM Bus Frequency Configurations
Core Frequency
667 MHz 600 MHz 533 MHz 500 MHz
SDR Interface Frequency Divider
5 5 4 4
SDR Interface Frequency
133 MHz 120 MHz 133 MHz 125 MHz
SDR Data Rate
133 MHz 120 MHz 133 MHz 125 MHz
With LongRun enabled, the core frequency is lowered during times when peak performance is not required. When the core frequency changes, the SDR SDRAM interface frequency is recalculated to match the new core frequency setting. For example, a 600 MHz device with a 120 MHz memory interface may have a LongRun setting of 533 MHz with a 133 MHz memory interface. Therefore, TM5400/TM5600-based systems that use LongRun must support the entire SDR SDRAM interface frequency range up to 133 MHz.
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1.3 PCI Interface
The TM5400/TM5600 PCI bus is revision 2.1 compliant. The PCI bus is 32 bits wide, operates at 33 MHz and is compatible with 3.3V levels (but is not 5V tolerant). The PCI controller on the TM5400/TM5600 provides a PCI host bridge, the central resource and a DMA controller. The TM5400/TM5600 PCI bus can sustain 132 Mbytes/sec bursts for reads and writes on 4 kByte blocks. The PCI controller snoops ahead on PCI-to-DRAM reads and writes. The 16 DWORD CPU-to-PCI write buffer converts sequential memory mapped I/O writes to PCI bursts. The DMA controller handles PCI-to-DRAM reads and writes. The 16 DWORD PCI-to-DRAM write buffer converts one 16 DWORD burst to eight separate address/data pairs. The 16 DWORD DRAM-to-PCI read ahead buffer permits continuation of read ahead after hitting in the buffer. The PCI controller tri-states the PCI bus when hot docking.
1.3.1
PCI Bus Commands
The TM5400/TM5600 PCI controller, in conjunction with the Code Morphing software, supports the PCI bus commands listed in Table 5. If the CPU generates a shutdown, halt or stop grant condition, a PCI special cycle is generated. The shutdown cycle is propagated with 0000h in the message field, the halt cycle is propagated with 0001h in the message field, and the stop grant cycle is propagated with 0002h in the message field and 0012h in the message dependent data field.
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TABLE 5
PCI Bus Commands Supported
Command Encoding (P_C/BE#)
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Command Type
Initiator Support
Yes Yes Yes Yes --Yes Yes --Yes Yes No No No No
Target Support
Interrupt Acknowledge Special Cycle I/O Read I/O Write --Memory Read Memory Write --Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate
No No No No --Yes Yes --No No As a memory read No As a memory read As a memory write
1.3.2
Bus Arbitration
The PCI controller central resource includes an integrated arbiter which supports up to seven PCI masters including a PCI-to-ISA bridge. P_REQ#[5:0] and P_GNT#[5:0] are the arbitration handshake signals used by PCI masters other than the PCI-to-ISA bridge. The PCI-to-ISA bridge uses the P_HOLD# and P_HLDA# signals. The arbiter, in conjunction with the Code Morphing software, implements a two-tier rotating prioritybased scheme. The upper tier arbitrates among the three bus master categories of CPU, PCI devices, and PCI-to-ISA bridge. The lower tier arbitrates among the requesting PCI devices. The arbitration priority scheme is shown in Figure 2. When the PCI bus becomes idle, the arbiter "parks" the PCI bus on the CPU. If the bus is parked and the CPU and another bus master(s) request the bus simultaneously, the CPU is granted the bus regardless of the state of the upper tier priority queue.
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FIGURE 2
PCI Arbitration Priority Scheme
RESET
RESET CPU-PCI-ISA P_REQ#[5] Lower Tier Arbitration Priority Scheme PCI-ISA-CPU P_REQ#[4]
Upper Tier Arbitration Priority Scheme
ISA-PCI-CPU
P_REQ#[3]
CPU-PCI-ISA
P_REQ#[2]
PCI-ISA-CPU
P_REQ#[1]
ISA-PCI-CPU
P_REQ#[0]
CPU-PCI-ISA
PCI-ISA-CPU
Notes: 1. In the upper tier priority queue, upon each bus grant, the priority sequences move up one level and the top priority sequence moves to the lowest level. 2. In the upper tier priority queue, for each priority sequence, the left-most device has highest priority. 3. In the lower tier priority scheme, the last agent granted is always dropped to the bottom of the queue for the next arbitration cycle.
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1.4 Southbridge Sidebands
The TM5400/TM5600 provides access to seven southbridge sideband signals. These signals are driven/monitored by a southbridge device on the base platform and are used to guarantee PC-compatible functionality for resets, interrupts, floating point errors, and processor clock control.
1.5 Serial Interfaces
The TM5400/TM5600 processor incorporates three separate serial interfaces: * * * Debug interface Configuration ROM interface Code Morphing software boot ROM interface
The debug interface is a two-pin interface that may be used for debug purposes and to read configuration data from the SDR SDRAM during the boot process. The configuration data may be used to initialize the SDRAM. The configuration ROM interface is a two-pin interface used to read data from a serial ROM device. The configuration ROM contains hardware data that is used to initialize the TM5400/TM5600 on power-up. The contents of the configuration ROM determines the settings for the CPU and the SDRAM clocks, and the memory and PCI interface timing parameters. Once the PCI and SDRAM interfaces have been initialized, the configuration ROM controls the transfer of the Code Morphing software from the Code Morphing software flash memory to the SDRAM. Control is then transferred to the Code Morphing software and the configuration ROM is disabled. Transmeta will supply programming information for the configuration ROM. The recommended ROM device is the 93LC56B-I/ SN from Microchip Technology, Inc. The Code Morphing software boot ROM interface is a five-pin interface used to read data from a serial flash ROM. This interface may also be used for in-system reprogramming. The flash ROM device stores the Code Morphing software. During the boot process, the Code Morphing software is copied from the flash memory to the SDRAM. The Code Morphing software boot ROM interface supports up to 1 MByte of total storage using either two 512 kByte devices or a single 1 MByte device. Transmeta will supply programming information for the Code Morphing software boot ROM.
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1.6 Clocks
The TM5400/TM5600 input clock (CLKIN) is multiplied up by the CPU clock multiplier to generate the CPU core clock. For currently defined TM5400/TM5600 part numbers, CLKIN is assumed to be 66 MHz. With a 66 MHz CLKIN, a CPU clock multiplier of 7.5 is used for a 500 MHz core, 8 is used for a 533 MHz core, 9 is used for a 600 MHz core, and 10 is used for a 667 MHz core. The CPU core clock is divided down by the DDR and SDR clock dividers to generate the DDR SDRAM and SDR SDRAM interface clocks. See "DDR SDRAM Interface" on page 13 for additional information on DDR frequency settings and "SDR SDRAM Interface" on page 14 for information on SDR frequency settings. There is also a TM5400/TM5600 clock divider that must be initialized for the PCI interface. Since the PCI interface operates at 33 MHz, the PCI clock divider for a 500 MHz core is 15, for a 533 MHz core is 16, for a 600 MHz core is 18, and for a 667 MHz core is 20. The clock multiplier and divider values are programmed into the TM5400/TM5600 during initialization from data stored in the configuration ROM.
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1.7 Power Management
1.7.1 Power Management States
The TM5400/TM5600 in conjunction with the Code Morphing software, supports ACPIcompliant power management modes. Table 6 lists the state of the TM5400/TM5600 processor for each of the ACPI global system states. The TM5400/TM5600 power management states listed in Table 6 are defined in greater detail in Table 7 and the following paragraphs. The processor's power management states and state transitions are shown in Figure 3. TABLE 6
Power Management System States
ACPI System State
Processor State
Normal Normal/ Auto Halt Normal/ Quick Start Auto Halt Quick Start Deep Sleep Off Off Off Off
SDR SDRAM
Clock Generator
Running Running Running Running Running CLKIN stopped All clocks stopped Off Off Off
Delay to Return to C0 State1
0 < 260 ns < 2.8 s < 260 ns <2.8 ns < 20 s 10 ms + BIOS < 30 s
G0/S0/C0: Working G0/S0/C1: Working/Auto Halt G0/S0/C2: Working/Quick Start G1/S1/C1: Sleeping/Auto Halt G1/S1/C2: Sleeping/Quick Start G1/S1/C3: Sleeping/Deep Sleep G1/S3: Sleeping/Suspend to RAM G1/S4: Sleeping/Suspend to disk G2/S5: Soft off G3: Mechanical off 1.
Normal Normal Normal/ Self refresh Normal Self refresh Self refresh Self refresh Off Off Off
Delay times specified assume a 533 MHz processor and a 33 MHz PCI bus frequency.
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TABLE 7
TM5400/TM5600 Power Management States
P95 State
Normal Auto Halt Quick Start Deep Sleep
P95 Core
Running Stopped Stopped Stopped
SDRAM
Running Running Self refresh Self refresh
PCI Controller
Running Running Running Stopped
Entry Trigger
Normal operation Executing a HLT instruction Asserting STPCLK# Asserting SLEEP# and stopping CLKIN while in Quick Start state
Snoops
Serviced Serviced Serviced Not allowed
Interrupts
Serviced Serviced Latched Not allowed
Auto Halt The Auto Halt state is a low-power mode entered through the execution of the HLT instruction. The Auto Halt state is exited upon an interrupt (INTR, INIT#, SMI# or NMI) or assertion of RESET#. Snoops are serviced while in the Auto Halt state. Quick Start The Quick Start state is entered with the assertion of the STPCLK# input pin. While in Quick Start, snoops are serviced and interrupts are latched. Latched interrupts are serviced once the processor returns to the Normal state. Only one occurrence of an interrupt is latched while in Quick Start. If RESET# is asserted while in Quick Start, processor initialization occurs and then the processor returns to the Quick Start state if STPCLK# is still asserted. Deep Sleep The Deep Sleep state is the lowest power mode that the CPU can enter while maintaining its context. After entering Quick Start, the processor enters Deep Sleep when SLEEP# is asserted and the master clock input (CLKIN) is stopped. The PCI clock input (P_PCLK) may also be stopped. The TM5400/TM5600 internal PLL is shutdown while in Deep Sleep. Therefore, when the clocks are restarted to exit Deep Sleep, the system must allow time for PLL resynchronization to occur. Snoops are not serviced and interrupts are neither serviced nor latched while in Deep Sleep. RESET# is ignored while in Deep Sleep. CLKIN and P_PCLK should be stopped while in a logic low state.
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FIGURE 3
Power Management State Machine
Normal
HS = false2
STPCLK# asserted and Stop Grant bus cycle4
HLT and Halt bus cycle3,4
Halt break1
STPCLK# negated and HS = false2
SLEEP# asserted and CLKIN stopped (P_PCLK optional)
STPCLK# asserted and Stop Grant bus cycle4
Auto Halt
HS = true2 STPCLK# negated and HS = true2 Snoop occurs Snoop occurs
Quick Start
Deep Sleep
SDRAM in selfrefresh mode
Snoop serviced and HS = true2
SLEEP# negated and CLKIN on Notes: 1. Halt Break = INTR, INIT#, NMI, SMI#, or RESET# 2. HS = processor halt state 3. HLT = halt instruction executed 4. Halt bus cycle = PCI special cycle Stop Grant bus cycle = PCI special cycle
Snoop Service
Snoop serviced and HS = false2
1.7.2
SDRAM Power Saving Mode
In addition to the power management states defined in the previous section, the TM5400/ TM5600 provides an additional power saving mode for SDR SDRAM. Power Saving Mode may be enabled during normal operation by programming a TM5400/TM5600-specific PCI configuration register (CD_MISC for DDR SDRAM, SD_MISC for SDR SDRAM). In Power Saving Mode, the clock enable lines to the SDRAM are active only when the SDRAM is being accessed or refreshed. This mode decreases power dissipation, but increases the latency for a memory cycle by one SDRAM clock. Refer to the TM5400/TM5600 BIOS Programmer's Guide for additional information.
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1.8 Test and Debug
The TM5400/TM5600 provides a 5-pin JTAG interface that can be used for TM5400/ TM5600 testing. This interface supports IEEE 1149.1, EXTEST, BYPASS, and HiZ. Sample/preload instructions are implemented.
1.9 Supply Voltages
The TM5400/TM5600 processor requires four supply voltages. The core supply voltage (CVDD) varies from 1.2 to 1.6 volts nominally. Two I/O supply voltages are required: IOVDD is 3.3 volts, and IOVDD25 is 2.5 volts. There is also a single supply pin for the TM5400/ TM5600 PLL circuit. The PLL supply voltage (PLLVDD) must equal the core supply voltage.
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1.10 Power On Sequence
The sequence of operations required to power on the TM5400/TM5600 processor is listed below: 1. Apply power to the system. Allow CVDD, IOVDD, IOVDD25 and PLLVDD to reach minimum operating levels. During power up, the supplies should ramp within 250 ms of each other. See "Power On Specifications" on page 60 for additional information. RESET#, P_PCI_RST# and PWRGOOD should all be held low during this time. With PWRGOOD at a low level, the TM5400/TM5600 processor is in a self-protecting mode. 2. Assert PWRGOOD. Assert PWRGOOD after all power supplies achieve 95% of their final voltage. 3. Begin toggling CLKIN. At or before the assertion of PWRGOOD, begin toggling CLKIN. 4. Deassert P_PCI_RST# and RESET#. P_PCI_RST# must be held low until at least 1 ms after CLKIN begins to toggle. It also must be held low until at least 1 ms after the PWRGOOD rising edge. 5. Load the TM5400/TM5600 mode bits from the configuration ROM. Once P_PCI_RST# is deasserted, the TM5400/TM5600 begins reading data from the off-chip configuration ROM using the CFG_SCLK and CFG_SDATA pins. The frequency of CFG_SCLK is 920 kHz (CLKIN/72). The TM5400/TM5600 begins reading the configuration ROM by sending an eleven-bit sequence of 11000000000. This sequence tells the configuration ROM to begin supplying data starting at address 0. There is a 1 clock delay to allow the direction of the CFG_SDATA pin to change from driving to receiving. The TM5400/TM5600 then issues 112 CFG_SCLKs to read the contents of the configuration ROM. The entire sequence completes in approximately 130 s. 6. Complete internal reset sequence. The TM5400/TM5600 internal reset sequence continues for approximately 800 ms plus an additional 64 internal clock cycles after the rising edge of RESET#. The TM5400/TM5600 then fetches its first instruction from either the serial boot ROM or from the PCI bus as determined by an internal mode bit.
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Chapter 2
Pin Description
The following paragraphs document the signal definitions, pin assignments, and footprint for the TM5400/TM5600 processor.
2.1 Signal Definitions
Table 8 provides a summary of the TM5400/TM5600 signals. Table 9 through Table 22 describe the function of each signal on the TM5400/TM5600. Pins that are designated as "reserved" may have an internal electrical connection. Therefore, unless specified otherwise in Table 20, there should be no external electrical connection to the TM5400/ TM5600 reserved pins. Table 14 lists the memory address translation that corresponds to the various SDRAM devices supported by the TM5400/TM5600.
TABLE 8 Signal Summary
Signal Group
SDR SDRAM DDR SDRAM PCI Southbridge Sidebands Serial Interfaces Master Clock and Reset Power Management Miscellaneous JTAG Power Ground Reserved TOTAL
Quantity
102 109 62 6 9 2 5 9 5 64 76 25 474
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TABLE 9
DDR SDRAM Interface Signals
Signal Name C_A[12:0] C_BA[1:0] C_CAS#
Type
O O O
Qty
13 2 1
Description
Memory Address. These pins carry row and column addressing information. Bank Address. These pins carry the bank address for the DDR SDRAM devices. Column Address Strobe. When asserted low, enables latching of the column address on the positive edge of the next clock. Clock Enable. When deasserted, the SDRAMs enter power down mode. C_CKE[1] and C_CKE[0] are identical, provided for loading; each drives one block. SDRAM Clocks. Differential clocks for the multiple banks of SDRAM. All SDRAM operations are synchronized to the clock. Chip Select. An SDRAM row is selected when its C_CS# pin is asserted low. Memory Data. This is the 64-bit data bus to the DDR SDRAMs. Data Mask. Used during read or write operations, one C_DQMB pin per data byte. Data Strobe. Used to capture data at the processor and SDRAM. When sending data to SDRAM, the strobe signal is centered to the data. When receiving data from SDRAM, the strobe is edge aligned to the data. Row Address Strobe. When asserted low, enables latching of the row address on the positive edge of the next clock. Voltage Reference. Reference voltage for the DDR SDRAM interface inputs. Used for SSTL_2 interface. Memory Write Enable. Enables write operations to the DDR SDRAMs.
C_CKE[1:0]
O
2
C_CLKA, C_CLKA#, C_CLKB, C_CLKB# C_CS#[3:0] C_DQ[63:0] C_DQMB[7:0] C_DQS[7:0]
O
4
O I/O O I/O
4 64 8 8
C_RAS#
O
1
C_VREF C_WE#
I O
1 1
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TABLE 10
Logical Alignment of DDR Byte Enables, Data Strobes and Data Bits
Byte Enable C_DQMB[0] C_DQMB[1] C_DQMB[2] C_DQMB[3] C_DQMB[4] C_DQMB[5] C_DQMB[6] C_DQMB[7]
Data Strobe C_DQS[0] C_DQS[1] C_DQS[2] C_DQS[3] C_DQS[4] C_DQS[5] C_DQS[6] C_DQS[7]
Data Bits C_DQ[7:0] C_DQ[15:8] C_DQ[23:16] C_DQ[31:24] C_DQ[39:32] C_DQ[47:40] C_DQ[55:48] C_DQ[63:56]
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TABLE 11
SDR SDRAM Interface Signals
Signal Name S_A[12:0] S_BA[1:0] S_CAS#
Type
O O O
Qty
13 2 1
Description
Memory Address. These pins carry row and column addressing information. Bank Address. These pins carry the bank address for the SDR SDRAM. Column Address Strobe. When asserted low, enables latching of the column address on the positive edge of the next clock. Clock Enable. When deasserted, the SDRAMs enter power down mode. Each S_CKE output drives up to 2 blocks. SDRAM Clocks. Clocks for the multiple rows of SDRAM.
S_CKE[1:0] S_CLK[3:0]
O O
2 4
S_CLK[3:0] are identical, provided for loading; each
drives one row.
S_CLKIN
I
1
Clock input. Return of S_CLKOUT used to calibrate the board delay of S_CLK[3:0] to the actual SDR SDRAM devices. Clock output. Clock output used in conjunction with
S_CLKOUT
O
1
S_CLKIN to calibrate the board delay of S_CLK[3:0] to
the actual SDR SDRAM devices.
S_CS#[3:0]
O
4
Chip Select. An SDRAM block is selected when its S_CS# pin is asserted low. S_CS#[1:0] are used for slot 0, and S_CS#[3:2] are used for slot 1. Memory Data. This is the 64-bit data bus to the SDRAM. Data Mask. Used during read or write operations, one
S_DQ[63:0] S_DQMB[7:0] S_RAS# S_WE#
I/O O O O
64 8 1 1
S_DQMB pin per data byte.
Row Address Strobe. When asserted low, enables latching of the row address on the positive edge of the next clock. Memory Write Enable. Enables write operations to the SDRAMs.
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TABLE 12
Logical Alignment of SDR Clocks, Clock Enables, and Chip Selects
Clock
Any S_CLK Any S_CLK Any S_CLK Any S_CLK
Clock Enable S_CKE[0] S_CKE[0] S_CKE[1] S_CKE[1]
Chip Select S_CS#[0] S_CS#[1] S_CS#[2] S_CS#[3]
TABLE 13
Logical Alignment of SDR Byte Enables and Data Bits
Byte Enable S_DQMB[0] S_DQMB[1] S_DQMB[2] S_DQMB[3] S_DQMB[4] S_DQMB[5] S_DQMB[6] S_DQMB[7]
Data Bits S_DQ[7:0] S_DQ[15:8] S_DQ[23:16] S_DQ[31:24] S_DQ[39:32] S_DQ[47:40] S_DQ[55:48] S_DQ[63:56]
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TABLE 14
Memory Address Translations
SDRAM Device Config1
16M / 2Bank: 1M x 16 2M x 8 4M x 4 64M / 4Bank: 2M x 32 4M x 16 8M x 8 16M x 4 128M / 4Bank: 4M x 32 8M x 16 16M x 8 32M x 4 256M / 4Bank: 8M x 32 16M x 16 32M x 8 64M x 4 1. 2.
CS#
BS1
BS0
C102
C09
C08
C(07-00)
R12
R11
R(10-00)
A23 A24 A25 A24 A25 A26 A27 A25 A26 A27 A28 A26 A27 A28 A29
---A23 A23 A23 A23 A23 A23 A23 A23 A23 A23 A23 A23
A11 A11 A11 A11 A11 A11 A11 A11 A11 A11 A11 A11 A11 A11 A11
----------A27 ---A28
--A24 ---A26 --A26 A26 --A27 A27
-A23 A23 --A25 A25 -A25 A25 A25 -A26 A26 A26
A(10-03) A(10-03) A(10-03) A(10-03) A(10-03) A(10-03) A(10:03) A(10-03) A(10-03) A(10-03) A(10-03) A(10-03) A(10-03) A(10-03) A(10-03)
-------A25 A25 A25 A25 A25 A25 A25 A25
----A24 A24 A24 A24 A24 A24 A24 A24 A24 A24 A24
A(22-12) A(22-12) A(22-12) A(22-12) A(22-12) A(22-12) A(22-12) A(22-12) A(22-12) A(22-12) A(22-12) A(22-12) A(22-12) A(22-12) A(22-12)
SDRAM device configuration is as follows: nM, xB = n Mbits, x banks. Column address 10 (C10) is sent out on address pin 11 during CAS cycle rather than address pin 10.
Key: CS# = Chip select or side select Bn = Bank select Cnn = SDRAM column address Rnn = SDRAM row address Ann = Processor address nn
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TABLE 15
PCI Interface Signals
Signal Name P_AD[31:0] P_C/BE#[3:0]
Type
I/O I/O
Qty
32 4
Description
Address/Data. The address is driven with P_FRAME#, and data is written or read with subsequent clocks. Command/Byte Enable. Command is driven with P_FRAME#. Byte enables correspond with the appropriate data on the PCI during read and write data cycles. Clock Run. This signal is open drain, and an external 2.7K resistor is required. When asserted low, the PCI clock is enabled to run. Device Select. Driven when a PCI initiator is accessing SDRAM. Frame. Asserted active low to indicate the beginning of a PCI access (address phase). Forced inactive high to indicate that another transfer is desired by the initiator of the cycle. Grant. Permission is given for a master to use the PCI bus. PCI Hold Acknowledge. Driven to a bridge device in response to its P_HOLD# request to indicate that the bridge can take control of the PCI. PCI Hold. Asserted by an expansion bridge to request use of the PCI bus. Initiator Ready. Asserted by the initiator to indicate that it is ready for data transfer. Lock. While asserted, the currently accessed PCI resource is locked. Parity. Single bit representing the parity of lines P_AD[31:0] and P_C/BE#[3:0]. Reset. Asynchronously resets the module PCI interface and North Bridge, and puts all PCI signals into tristate. PCI Clock. PCI Parity Error. PCI Request. A PCI master asserts this to request access to the PCI bus. System error. Stop. Asserted by a target device to request the master stop driving the PCI bus. Target Ready. Asserted by the target to indicate that it is ready for a data transfer.
P_CLKRUN#
I/O
1
P_DEVSEL# P_FRAME#
I/O I/O
1 1
P_GNT#[5:0] P_HLDA#
O O
6 1
P_HOLD# P_IRDY# P_LOCK# P_PAR P_PCI_RST# P_PCLK P_PERR# P_REQ#[5:0] P_SERR# P_STOP# P_TRDY#
I I/O I/O I/O I/O I I/O I I I/O I/O
1 1 1 1 1 1 1 6 1 1 1
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TABLE 16
Southbridge Sideband Interface Signals
Signal Name FERR# IGNNE#
Type
O I
Qty
1 1
Description
Floating Point Unit Error. Driven by the processor when a floating point error is detected. Ignore Numeric Error. Driven by the southbridge, this signal instructs the processor to ignore numeric exceptions and to continue to execute non-control floating point instructions. Initialize. Asserted by the southbridge for system initialization. If INIT# is asserted, the processor resets internal integer registers. Interrupt. Driven by the southbridge to the processor to indicate that a maskable interrupt from a device is pending. Non-Maskable Interrupt. Forces a non-maskable interrupt to the processor. System Management Interrupt. This input requests that an interrupt be serviced for system management functions such as power control.
INIT#
I
1
INTR NMI SMI#
I I I
1 1 1
TABLE 17
Serial Interface Signals
Signal Name S_SCLK S_SDATA CFG_SCLK
Type
I/O I/O O
Qty
1 1 1
Description
Serial Clock. Clock for debug interface to SDR SDRAM. Serial Data. Data for debug interface to SDR SDRAM. Configuration ROM Clock. Clock for the serial interface to the configuration ROM. Reading the configuration ROM is initiated by deassertion of P_RST# and is clocked at a frequency of CLKIN x 1/72. Configuration ROM Data. Data for the serial interface to the configuration ROM. Code Morphing Software Boot ROM Chip Selects. When using two 512 kByte devices, SROM_CS#[0] selects the lower 512 kBytes and SROM_CS#[1] selects the upper 512 kBytes. When using a single 1 MByte device, only SROM_CS#[0] is used. Code Morphing Software Boot ROM Clock. Clock from TM5400/TM5600 to Code Morphing software boot ROM. Code Morphing Software Boot ROM Serial Data In. Data from Code Morphing software boot ROM to TM5400/TM5600. Code Morphing Software Boot ROM Serial Data Out. Data from TM5400/TM5600 to Code Morphing software boot ROM.
CFG_SDATA SROM_CS#[1:0]
I/O O
1 2
SROM_SCLK
O
1
SROM_SIN
I
1
SROM_SOUT
O
1
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TABLE 18
Master Clock and Reset Signals
Signal Name CLKIN RESET#
Type
I I
Qty
1 1
Description
Clock In. TM5400/TM5600 master clock input. Reset. TM5400/TM5600 master reset input.
TABLE 19
Power Management Interface Signals
Signal Name PWRGOOD SLEEP#
Type
I I
Qty
1 1
Description
Power Good. Indicates that the input clock and power supplies are stable. Sleep. Used to put the TM5400/TM5600 into a low power deep sleep mode. Turns off PCI interface by stopping PCI clock and tri-stating PCI pins. Allows P_PCLK to be stopped. Stop Clock. Stops the internal clocks of the TM5400/ TM5600 with the exception of the internal master controller and the PCI controller. Thermal Diode. Cathode for the internal thermal diode used to monitor the die temperature. Thermal Diode. Anode for the internal thermal diode used to monitor the die temperature.
STPCLK#
I
1
DIODE_CATHODE DIODE_ANODE
O I
1 1
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TABLE 20
Miscellaneous Signals
Signal Name EPROMA[2:0]
Type
O
Qty
3
Description
BIOS ROM Address Bits. EPROMA[2:1] are used as address bits [19:18] for the BIOS EPROM. EPROMA[0] is not used, and there should be no electrical connection to it. Debug Input. This pin is used for debugging purposes only. For proper operation, DEBUG_INT should be connected to GND through a 4.7K resistor. Voltage Regulator Control. These pins are programmable outputs intended to be used as control inputs to the system voltage regulator. They facilitate fine tuning of the core voltage supply (CVDD) to minimize power or maximize performance. Reserved Test Inputs. For proper operation, these reserved pins should be connected as follows: 4.7K pull-down:
DEBUG_INT
I
1
VRDA[4:0]
O
5
I
12
Reserved (E7) Reserved (G13) Reserved (W11)
Reserved (E7) Reserved (G13) Reserved (W11) 4.7K pull-up to IOVDD:
Reserved (F7) Reserved (G1) Reserved (G2) Reserved (H5) Reserved (H6) Reserved (V1) Reserved (V2) Reserved (V3) Reserved (W6)
Reserved (F7) Reserved (G1) Reserved (G2) Reserved (H5) Reserved (H6) Reserved (V1) Reserved (V2) Reserved (V3) Reserved (W6)
There should be no external electrical connection to all other reserved pins.
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TABLE 21
JTAG Interface Signals
Signal Name TCK TDI TDO TMS TRST#
Type
I I O I I
Qty
1 1 1 1 1
Description
Test Clock. Test Data In. This pin has an internal pull-up. Test Data Out. Test Mode Select. This pin has an internal pull-up. Test Reset. TRST# is an asynchronous input that resets the test logic in the TM5400/TM5600. This pin has an internal pull-up. TRST# must be connected to RESET# if the JTAG interface pins are not going to be used.
TABLE 22
Power and Ground Signals
Signal Name CVDD IOVDD IOVDD25 PLLVDD VSS
Qty
23 28 12 1 76
Description
Core Supply. CVDD = 1.2-1.6V nominal. 3.3V I/O Supply. IOVDD = 3.3V nominal. 2.5V I/O Supply. IOVDD25 = 2.5V nominal. PLL Supply. PLLVDD = CVDD. Ground.
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2.2 I/O Signal Listings
The following tables summarize signal characteristics for each of the I/O signal pins. Table 23 lists the input signals, Table 24 lists the output signals and Table 25 lists the bidirectional signals.
TABLE 23 Input Only Signals
Signal Name C_VREF CLKIN DEBUG_INT DIODE_ANODE IGNNE# INIT# INTR NMI P_HOLD# P_PCLK P_SERR# P_REQ#[5:0] PWRGOOD RESET# S_CLKIN SLEEP# SMI# SROM_SIN STPCLK# TCK TDI TMS TRST#
Internal Resistor
Pull-up Pull-up Pull-up
Active Level
High Low Low High High Low Low Low High Low Low Low Low High High Low
Clock Domain
Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous
DC Specs
Table 29 Table 32 Table 45 Table 35 Table 32 Table 32 Table 32 Table 32 Table 34 Table 34 Table 34 Table 34 Table 32 Table 32 Table 32 Table 32 Table 32 Table 32 Table 32 Table 32 Table 32 Table 32 Table 32
AC Specs
"3.5.2", "3.5.3" "3.5.7" "3.5.7" "3.5.7" "3.5.7" "3.5.6" "3.5.2", "3.5.3", "3.5.6" "3.5.6" "3.5.6" "3.5.2", "3.5.7" "3.5.2" "3.5.3", "3.5.5" "3.5.7" "3.5.7" "3.5.9" "3.5.7" "3.5.11" "3.5.11" "3.5.11" "3.5.11"
P_PCLK
-
P_PCLK P_PCLK
Asynchronous Asynchronous Asynchronous Asynchronous
SROM_SCLK
Asynchronous -
TCK TCK
Asynchronous
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TABLE 24
Output Only Signals
Signal Name C_A[12:0] C_BA[1:0] C_CAS# C_CKE[1:0] C_CLKA, C_CLKA#, C_CLKB, C_CLKB# C_CS#[3:0] C_DQMB[7:0] C_RAS# C_WE# CFG_SCLK DIODE_CATHODE EPROMA[2:0] FERR# P_GNT#[5:0] P_HLDA# S_A[12:0] S_BA[1:0] S_CAS# S_CKE[1:0] S_CLK[3:0] S_CLKOUT S_CS#[3:0] S_DQMB[7:0] S_RAS# S_WE# SROM_CS#[1:0] SROM_SCLK SROM_SOUT TDO VRDA[4:0]
1.
Pin Type
Tri-state Tri-state Tri-state Tri-state Tri-state
Active Level
High Low High -
Clock C_CLK C_CLK C_CLK C_CLK -
Reset State
1/0 1/0 1 0 Toggle
Doze State1
Hi-Z Hi-Z Hi-Z 0 Hi-Z
DC Specs
Table 33 Table 33 Table 33 Table 33 Table 33
AC Specs
"3.5.4" "3.5.4" "3.5.4" "3.5.4" "3.5.4"
Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Open drain Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Open drain
Low High Low Low High Low Low Low High Low High Low High Low Low Low -
C_CLK C_CLK C_CLK C_CLK Asynch. Asynch. P_PCLK P_PCLK S_CLKIN S_CLKIN S_CLKIN S_CLKIN S_CLKIN S_CLKIN S_CLKIN S_CLKIN SROM_SCLK SROM_SCLK TCK -
1 0 1 1 Hi-Z Lo-Z 0 Hi-Z Hi-Z Hi-Z 1 1 1 0 Toggle Toggle 1 1 1 1 Hi-Z Hi-Z Hi-Z Hi-Z 1/0
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Lo-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Lo-Z
Table 33 Table 33 Table 33 Table 33 Table 32 Table 35 Table 32 Table 32 Table 34 Table 34 Table 32 Table 32 Table 32 Table 32 Table 32 Table 32 Table 32 Table 32 Table 32 Table 32 Table 32 Table 32 Table 32 Table 32 Table 32
"3.5.4" "3.5.4" "3.5.4" "3.5.4" "3.5.10" "3.5.6" "3.5.6" "3.5.5" "3.5.5" "3.5.5" "3.5.5" "3.5.5" "3.5.5" "3.5.5" "3.5.5" "3.5.5" "3.5.5" "3.5.9" "3.5.9" "3.5.9" "3.5.11" -
See Table 25, Note 1.
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TABLE 25
Bidirectional Signals
Signal Name C_DQ[63:0] C_DQS[7:0] CFG_SDATA P_AD[31:0] P_C/BE#[3:0] P_CLKRUN# P_DEVSEL# P_FRAME# P_IRDY# P_LOCK# P_PAR P_PCI_RST# P_PERR# P_STOP# P_TRDY# S_DQ[63:0] S_SCLK S_SDATA
1.
Pin Type
Active Level
Low
Clock C_CLK C_CLK CFG_SCLK P_PCLK P_PCLK P_PCLK P_PCLK P_PCLK P_PCLK P_PCLK P_PCLK Asynch. P_PCLK P_PCLK P_PCLK S_CLKIN S_SCLK
Reset State
Hi-Z Hi-Z Hi-Z 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Doze State1
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
DC Specs
Table 33 Table 33 Table 32 Table 34 Table 34 Table 34 Table 34 Table 34 Table 34 Table 34 Table 34 Table 34 Table 34 Table 34 Table 34 Table 32 Table 32 Table 32
AC Specs
"3.5.4" "3.5.4" "3.5.10" "3.5.6" "3.5.6" "3.5.6" "3.5.6" "3.5.6" "3.5.6" "3.5.6" "3.5.6" "3.5.2", "3.5.6" "3.5.6" "3.5.6" "3.5.6" "3.5.5" "3.5.8" "3.5.8"
Open drain
Low Low Low Low Low High Low Low Low Low -
Open drain Open drain
-
Doze state refers to the state of the signal during low-power modes when the specific interface is disabled. In the case of the SDRAM interfaces, the doze state refers to the state of the signal while the SDRAM is in self-refresh.
2.3 Footprint and Pin Assignments
Figure 4 shows the TM5400/TM5600 package footprint. Table 26 and Table 27 list the pin assignments for each signal on the TM5400/TM5600.
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FIGURE 4
Package Footprint - Top Down View
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
Ground (76) PLL VDD (1)
Core VDD (23) IO VDD 3.3V (28)
I/O signals and reserved IO VDD 2.5V (12)
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TABLE 26
TM5400/TM5600 Pin Assignments - Sorted by Pin Number
Pin No.
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15
Signal Name
No Pin
Pin No.
B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
Signal Name DIODE_CATHODE P_AD[3] P_AD[2] P_AD[0] S_DQ[53] S_DQ[55] GND S_DQ[31] S_DQ[30] IOVDD CLKIN GND P_AD[28] GND P_AD[21] GND P_STOP# IOVDD P_AD[12] P_AD[7] GND P_AD[1] P_HOLD# S_DQ[51] S_DQ[54] IOVDD S_DQ[28] S_DQ[21] S_DQ[23]
Reserved
Pin No.
D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 F1 F2 F3 F4 F5 F6 F7
Signal Name P_AD[20] P_SERR# P_AD[14] P_AD[10] P_AD[4] IOVDD P_REQ#[1] P_REQ#[0] S_DQ[50] S_DQ[52] S_DQ[26] S_DQ[27] S_DQ[22] S_DQ[19]
Reserved (E7)
S_DQ[59] S_DQ[57] S_DQ[60] S_DQ[56] S_SCLK PLLVDD CFG_SDATA P_AD[30] P_AD[31] P_C/BE#[2] P_C/BE#[0] P_FRAME# P_LOCK# P_GNT#[3] P_GNT#[1] P_DEVSEL# DIODE_ANODE TMS S_DQ[63] S_DQ[62] S_DQ[61] S_DQ[58] S_DQ[29] S_SDATA CFG_SCLK P_AD[27] P_AD[29] P_C/BE#[3] P_C/BE#[1] P_IRDY# P_TRDY# P_PAR P_AD[15]
P_PCI_RST# P_AD[25] P_AD[22] P_AD[18] P_AD[16] P_HLDA# P_AD[13] P_AD[9] P_AD[5] P_AD[6] P_REQ#[3] P_REQ#[2] S_DQ[48] S_DQ[49] S_DQ[25] S_DQ[24] S_DQ[20] GND
Reserved (F7)
SLEEP# P_AD[26] P_AD[23] P_AD[19]
42
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TM5400/TM5600 Data Book
November 1, 2000
TABLE 26
TM5400/TM5600 Pin Assignments - Sorted by Pin Number (Continued)
Pin No.
F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 H1 H2 H3 H4
Signal Name P_PCLK P_AD[24] GND P_AD[17] P_PERR# P_GNT#[2] GND P_AD[11] P_AD[8] P_GNT#[5] P_REQ#[5] P_REQ#[4]
Reserved (G1) Reserved (G2)
Pin No.
H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 K1
Signal Name
Reserved (H5) Reserved (H6)
Pin No.
K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17
Signal Name S_A[12]
Reserved Reserved Reserved
IOVDD GND CVDD GND CVDD GND IOVDD DEBUG_INT IGNNE# FERR# NMI STPCLK# RESET# S_CKE[1] S_CKE[0] IOVDD
Reserved Reserved
GND IOVDD GND CVDD GND CVDD GND IOVDD GND SROM_CS#[0] C_DQ[32] SROM_SIN SROM_SOUT C_VREF S_BA[1] S_BA[0] GND S_CLK[3]
Reserved
GND S_DQ[16] S_DQ[18] S_DQ[17] PWRGOOD GND TRST# GND
Reserved
IOVDD GND IOVDD GND CVDD GND IOVDD GND IOVDD EPROMA[1] EPROMA[0] IOVDD P_CLKRUN# EPROMA[2] S_A[11]
GND
Reserved (G13)
IOVDD GND CVDD GND CVDD GND CVDD GND IOVDD SROM_CS#[1] SROM_SCLK GND
SMI# P_GNT#[0] P_GNT#[4] GND INIT# INTR S_DQMB[7] S_DQMB[6] S_DQMB[3] S_DQMB[2]
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TM5400/TM5600 Data Book
TABLE 26
TM5400/TM5600 Pin Assignments - Sorted by Pin Number (Continued)
Pin No.
L18 L19 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14
Signal Name C_DQ[31] C_DQ[30] S_A[5] S_A[10] S_CLK[0] S_CLK[1] S_CLK[2] GND IOVDD GND CVDD GND CVDD GND IOVDD25 GND C_DQ[33] C_DQ[34] C_DQ[35] C_DQ[29] C_DQ[28] S_A[7] S_A[9] IOVDD S_A[1] S_A[4] IOVDD GND CVDD GND CVDD GND CVDD GND IOVDD25
Pin No.
N15 N16 N17 N18 N19 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11
Signal Name C_DQ[36] C_DQ[37] IOVDD25 C_DQ[27] C_DQ[26] S_A[6] S_A[8] S_A[0] S_A[3] S_WE# GND IOVDD GND CVDD GND CVDD GND IOVDD25 GND C_DQ[38] C_DQ[39] C_DQS[4] C_DQ[25] C_DQ[24] Reserved Reserved GND Reserved S_RAS# IOVDD GND CVDD GND CVDD GND
Pin No.
R12 R13 R14 R15 R16 R17 R18 R19 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 U6 U7 U8
Signal Name CVDD GND IOVDD25 C_DQMB[4] C_DQMB[5] GND C_DQS[3] C_DQMB[3] S_CS#[2] S_CS#[3] S_CS#[1] S_CS#[0] Reserved GND IOVDD GND CVDD GND CVDD GND IOVDD25 GND C_DQS[5] C_DQ[40] C_DQ[41] C_DQMB[2] C_DQS[2] S_DQMB[0] S_DQMB[5] IOVDD S_DQMB[1] S_DQMB[4] IOVDD GND IOVDD
44
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TM5400/TM5600 Data Book
November 1, 2000
TABLE 26
TM5400/TM5600 Pin Assignments - Sorted by Pin Number (Continued)
Pin No.
U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5
Signal Name GND CVDD GND IOVDD25 GND IOVDD25 C_DQ[42] C_DQ[43] IOVDD25 C_DQ[23] C_DQ[22]
Reserved (V1) Reserved (V2) Reserved (V3)
Pin No.
W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 AA1 AA2
Signal Name
Reserved (W6)
Pin No.
AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18
Signal Name S_DQ[12] S_DQ[11] S_DQ[3] S_DQ[32] C_A[7] C_A[9] C_CLKB C_CLKA C_DQ[62] C_DQ[60] C_DQ[57] C_DQS[7] C_DQ[52] C_DQ[54] C_DQ[53] C_DQ[15] C_DQ[14] S_DQ[41] S_DQ[40] IOVDD S_DQ[1] S_DQ[2] S_CLKIN C_A[6] C_A[8] C_A[12] C_CLKB# C_DQ[63] C_DQ[61] C_DQ[58] C_DQ[56] C_DQMB[6] C_DQ[55] IOVDD25 C_DQ[13]
TCK GND TDI GND
Reserved (W11)
GND VRDA[4] VRDA[3] C_DQ[47] C_DQ[48] GND C_DQ[19] C_DQ[18] S_DQ[45] S_DQ[44] S_DQ[14] S_DQ[13] S_DQ[4] GND C_CKE[1] C_CS#[1] C_CS#[2] GND C_CS#[3] VRDA[0] VRDA[1] GND C_DQ[49] C_DQ[50] C_DQ[51] C_DQ[17] C_DQ[16] S_DQ[43] S_DQ[42]
S_CAS# S_A[2] S_CLKOUT IOVDD GND CVDD GND CVDD GND IOVDD25 VRDA[2] C_DQ[44] C_DQ[45] C_DQ[46] C_DQ[21] C_DQ[20] S_DQ[47] S_DQ[46] GND S_DQ[15] S_DQ[0]
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November 1, 2000
TM5400/TM5600 Data Book
TABLE 26
TM5400/TM5600 Pin Assignments - Sorted by Pin Number (Continued)
Pin No.
AB19 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19
Signal Name C_DQ[12] S_DQ[9] S_DQ[8] GND S_DQ[5] S_DQ[33] IOVDD C_A[5] GND C_A[11] GND C_CLKA# GND C_DQ[59] IOVDD25 C_DQMB[7] C_DQS[6] GND C_DQ[11] C_DQ[10]
Pin No.
AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19
Signal Name S_DQ[10] S_DQ[7] S_DQ[6] S_DQ[35] S_DQ[34] C_A[4] C_A[2] C_A[0] C_BA[1] C_CS#[0] C_CAS# C_DQ[0] C_DQ[2] C_DQ[4] C_DQ[6] C_DQS[0] C_DQMB[1] C_DQ[9] C_DQ[8]
Pin No.
AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19
Signal Name TDO S_DQ[39] S_DQ[36] S_DQ[38] S_DQ[37] C_CKE[0] C_A[3] C_A[1] C_A[10] C_BA[0] C_RAS# C_WE# C_DQ[1] C_DQ[3] C_DQ[5] C_DQ[7] C_DQMB[0] C_DQS[1]
Reserved
46
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TM5400/TM5600 Data Book
November 1, 2000
TABLE 27
TM5400/TM5600 Pin Assignments - Sorted by Signal Name
Signal Name C_A[0] C_A[1] C_A[2] C_A[3] C_A[4] C_A[5] C_A[6] C_A[7] C_A[8] C_A[9] C_A[10] C_A[11] C_A[12] C_BA[0] C_BA[1] C_CAS# C_CKE[0] C_CKE[1] C_CLKA C_CLKA# C_CLKB C_CLKB# C_CS#[0] C_CS#[1] C_CS#[2] C_CS#[3] C_DQ[0] C_DQ[1] C_DQ[2] C_DQ[3] C_DQ[4] C_DQ[5] C_DQ[6] C_DQ[7]
Pin No.
AD8 AE8 AD7 AE7 AD6 AC7 AB7 AA7 AB8 AA8 AE9 AC9 AB9 AE10 AD9 AD11 AE6 Y7 AA10 AC11 AA9 AB10 AD10 Y8 Y9 Y11 AD12 AE13 AD13 AE14 AD14 AE15 AD15 AE16
Signal Name C_DQ[8] C_DQ[9] C_DQ[10] C_DQ[11] C_DQ[12] C_DQ[13] C_DQ[14] C_DQ[15] C_DQ[16] C_DQ[17] C_DQ[18] C_DQ[19] C_DQ[20] C_DQ[21] C_DQ[22] C_DQ[23] C_DQ[24] C_DQ[25] C_DQ[26] C_DQ[27] C_DQ[28] C_DQ[29] C_DQ[30] C_DQ[31] C_DQ[32] C_DQ[33] C_DQ[34] C_DQ[35] C_DQ[36] C_DQ[37] C_DQ[38] C_DQ[39] C_DQ[40] C_DQ[41]
Pin No.
AD19 AD18 AC19 AC18 AB19 AB18 AA19 AA18 Y19 Y18 W19 W18 V19 V18 U19 U18 P19 P18 N19 N18 M19 M18 L19 L18 K16 M15 M16 M17 N15 N16 P15 P16 T16 T17
Signal Name C_DQ[42] C_DQ[43] C_DQ[44] C_DQ[45] C_DQ[46] C_DQ[47] C_DQ[48] C_DQ[49] C_DQ[50] C_DQ[51] C_DQ[52] C_DQ[53] C_DQ[54] C_DQ[55] C_DQ[56] C_DQ[57] C_DQ[58] C_DQ[59] C_DQ[60] C_DQ[61] C_DQ[62] C_DQ[63] C_DQMB[0] C_DQMB[1] C_DQMB[2] C_DQMB[3] C_DQMB[4] C_DQMB[5] C_DQMB[6] C_DQMB[7] C_DQS[0] C_DQS[1] C_DQS[2] C_DQS[3]
Pin No.
U15 U16 V15 V16 V17 W15 W16 Y15 Y16 Y17 AA15 AA17 AA16 AB16 AB14 AA13 AB13 AC13 AA12 AB12 AA11 AB11 AE17 AD17 T18 R19 R15 R16 AB15 AC15 AD16 AE18 T19 R18
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47
November 1, 2000
TM5400/TM5600 Data Book
TABLE 27
TM5400/TM5600 Pin Assignments - Sorted by Signal Name (Continued)
Signal Name C_DQS[4] C_DQS[5] C_DQS[6] C_DQS[7] C_RAS# C_VREF C_WE# CFG_SCLK CFG_SDATA CLKIN CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD DEBUG_INT DIODE_ANODE
Pin No.
P17 T15 AC16 AA14 AE11 K19 AE12 B7 A8 C7 H9 H11 J10 K9 K11 L8 L10 L12 M9 M11 N8 N10 N12 P9 P11 R8 R10 R12 T9 T11 U10 V9 V11 H14 A18
Signal Name DIODE_CATHODE EPROMA[0] EPROMA[1] EPROMA[2] FERR# GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Pin No.
B16 J16 J15 J19 H16 C3 C8 C10 C12 C17 F6 F10 F14 G3 G8 G10 G12 G17 H8 H10 H12 J7 J9 J11 J13 K6 K8 K10 K12 K14 L3 L7 L9 L11 L13
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Pin No.
L17 M6 M8 M10 M12 M14 N7 N9 N11 N13 P6 P8 P10 P12 P14 R3 R7 R9 R11 R13 R17 T6 T8 T10 T12 T14 U7 U9 U11 U13 V8 V10 V12 W3 W8
48
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TM5400/TM5600 Data Book
November 1, 2000
TABLE 27
TM5400/TM5600 Pin Assignments - Sorted by Signal Name (Continued)
Signal Name GND GND GND GND GND GND GND GND GND GND GND IGNNE# INIT# INTR IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD
Pin No.
W10 W12 W17 Y6 Y10 Y14 AC3 AC8 AC10 AC12 AC17 H15 G18 G19 C6 C14 D3 D17 H7 H13 J3 J6 J8 J12 J14 J17 K7 K13 L6 L14 M7 N3 N6 P7 R6
Signal Name IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD25 IOVDD25 IOVDD25 IOVDD25 IOVDD25 IOVDD25 IOVDD25 IOVDD25 IOVDD25 IOVDD25 IOVDD25 IOVDD25 NMI P_AD[0] P_AD[1] P_AD[2] P_AD[3] P_AD[4] P_AD[5] P_AD[6] P_AD[7] P_AD[8] P_AD[9] P_AD[10] P_AD[11] P_AD[12] P_AD[13] P_AD[14]
Pin No.
T7 U3 U6 U8 V7 AB3 AC6 M13 N14 N17 P13 R14 T13 U12 U14 U17 V13 AB17 AC14 H17 B19 C18 B18 B17 D16 E16 E17 C16 F16 E15 D15 F15 C15 E14 D14
Signal Name P_AD[15] P_AD[16] P_AD[17] P_AD[18] P_AD[19] P_AD[20] P_AD[21] P_AD[22] P_AD[23] P_AD[24] P_AD[25] P_AD[26] P_AD[27] P_AD[28] P_AD[29] P_AD[30] P_AD[31] P_C/BE#[0] P_C/BE#[1] P_C/BE#[2] P_C/BE#[3] P_CLKRUN# P_DEVSEL# P_FRAME# P_GNT#[0] P_GNT#[1] P_GNT#[2] P_GNT#[3] P_GNT#[4] P_GNT#[5] P_HLDA# P_HOLD# P_IRDY# P_LOCK# P_PAR
Pin No.
B15 E12 F11 E11 D11 D12 C11 E10 D10 F9 E9 D9 B8 C9 B9 A9 A10 A12 B11 A11 B10 J18 A17 A13 G15 A16 F13 A15 G16 F17 E13 C19 B12 A14 B14
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November 1, 2000
TM5400/TM5600 Data Book
TABLE 27
TM5400/TM5600 Pin Assignments - Sorted by Signal Name (Continued)
Signal Name P_PCI_RST# P_PCLK P_PERR# P_REQ#[0] P_REQ#[1] P_REQ#[2] P_REQ#[3] P_REQ#[4] P_REQ#[5] P_SERR# P_STOP# P_TRDY# PLLVDD PWRGOOD
Reserved Reserved (E7) Reserved (F7) Reserved (G1) Reserved (G2) Reserved Reserved (G13) Reserved (H5) Reserved (H6) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved (V1) Reserved (V2)
Pin No.
E8 F8 F12 D19 D18 E19 E18 F19 F18 D13 C13 B13 A7 G7 D7 E7 F7 G1 G2 G11 G13 H5 H6 J4 J5 K3 K4 K5 L5 R1 R2 R4 T5 V1 V2
Signal Name
Reserved (V3) Reserved (W6) Reserved (W11) Reserved
Pin No.
V3 W6 W11 AE19 H19 P3 N4 V5 P4 N5 M1 P1 N1 P2 N2 M2 K1 K2 L2 L1 V4 J2 J1 M3 M4 M5 L4 AB6 V6 T4 T3 T1 T2 W5 AB4
Signal Name S_DQ[2] S_DQ[3] S_DQ[4] S_DQ[5] S_DQ[6] S_DQ[7] S_DQ[8] S_DQ[9] S_DQ[10] S_DQ[11] S_DQ[12] S_DQ[13] S_DQ[14] S_DQ[15] S_DQ[16] S_DQ[17] S_DQ[18] S_DQ[19] S_DQ[20] S_DQ[21] S_DQ[22] S_DQ[23] S_DQ[24] S_DQ[25] S_DQ[26] S_DQ[27] S_DQ[28] S_DQ[29] S_DQ[30] S_DQ[31] S_DQ[32] S_DQ[33] S_DQ[34] S_DQ[35] S_DQ[36]
Pin No.
AB5 AA5 Y5 AC4 AD3 AD2 AC2 AC1 AD1 AA4 AA3 Y4 Y3 W4 G4 G6 G5 E6 F5 D5 E5 D6 F4 F3 E3 E4 D4 B5 C5 C4 AA6 AC5 AD5 AD4 AE3
RESET# S_A[0] S_A[1] S_A[2] S_A[3] S_A[4] S_A[5] S_A[6] S_A[7] S_A[8] S_A[9] S_A[10] S_A[11] S_A[12] S_BA[0] S_BA[1] S_CAS# S_CKE[0] S_CKE[1] S_CLK[0] S_CLK[1] S_CLK[2] S_CLK[3] S_CLKIN S_CLKOUT S_CS#[0] S_CS#[1] S_CS#[2] S_CS#[3] S_DQ[0] S_DQ[1]
50
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TM5400/TM5600 Data Book
November 1, 2000
TABLE 27
TM5400/TM5600 Pin Assignments - Sorted by Signal Name (Continued)
Signal Name S_DQ[37] S_DQ[38] S_DQ[39] S_DQ[40] S_DQ[41] S_DQ[42] S_DQ[43] S_DQ[44] S_DQ[45] S_DQ[46] S_DQ[47] S_DQ[48] S_DQ[49] S_DQ[50] S_DQ[51] S_DQ[52] S_DQ[53] S_DQ[54] S_DQ[55]
Pin No.
AE5 AE4 AE2 AB2 AB1 AA2 AA1 Y2 Y1 W2 W1 F1 F2 E1 D1 E2 C1 D2 C2
Signal Name S_DQ[56] S_DQ[57] S_DQ[58] S_DQ[59] S_DQ[60] S_DQ[61] S_DQ[62] S_DQ[63] S_DQMB[0] S_DQMB[1] S_DQMB[2] S_DQMB[3] S_DQMB[4] S_DQMB[5] S_DQMB[6] S_DQMB[7] S_RAS# S_SCLK S_SDATA
Pin No.
A5 A3 B4 A2 A4 B3 B2 B1 U1 U4 H4 H3 U5 U2 H2 H1 R5 A6 B6
Signal Name S_WE# SLEEP# SMI# SROM_CS#[0] SROM_CS#[1] SROM_SCLK SROM_SIN SROM_SOUT STPCLK# TCK TDI TDO TMS TRST# VRDA[0] VRDA[1] VRDA[2] VRDA[3] VRDA[4]
Pin No.
P5 D8 G14 K15 L15 L16 K17 K18 H18 W7 W9 AE1 A19 G9 Y12 Y13 V14 W14 W13
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51
November 1, 2000
TM5400/TM5600 Data Book
52
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TM5400/TM5600 Data Book
November 1, 2000
Chapter 3
Electrical Specifications
3.1 Absolute Maximum Ratings
TABLE 28
Absolute Maximum Ratings
Symbol CVDD IOVDD IOVDD25 PLLVDD Vin Iin Tstorage
Parameter
Core voltage 3.3V I/O voltage 2.5V I/O voltage
Minimum
-0.2 V -0.2 V -0.2 V -0.2 V 0.0 V -0.5 V -100 mA -55C
Maximum
2.35 V 3.6 V 3.6 V 2.35 V 3.465 V 3.96 V 100 mA 150C
PLL voltage IOVDD, IOVDD25 relative to CVDD, PLLVDD
Input voltage Input current Storage temperature
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November 1, 2000
TM5400/TM5600 Data Book
3.2 Recommended Operating Conditions
TABLE 29
Recommended Operating Conditions
Symbol CVDD, PLLVDD
Parameter
Core voltage, PLL voltage 500 MHz 533 MHz 600 MHz 667 MHz Minimum LongRun setting 300 MHz
Minimum
1.52 V
Nominal
1.6 V
Maximum
1.68 V
1.14 V 3.135 V 2.375 V 1.187 V GND 0C
1.2 V 3.3 V 2.5 V 0.5 x IOVDD25 -
1.26 V 3.465 V 2.625 V 1.312 V
IOVDD IOVDD25 C_VREF Vin Tj
3.3V I/O voltage 2.5V I/O voltage DDR SDRAM interface voltage reference Input voltage Junction temperature
IOVDD
85C
54
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3.3 Power and Current Specifications
TABLE 30 Parameter
Thermal design power 500 MHz 533 MHz 600 MHz 667 MHz Typical operating power 300-500 MHz 300-533 MHz 300-600 MHz 300-667 MHz Auto Halt power 300-500 MHz 300-533 MHz 300-600 MHz 300-667 MHz Quick Start power 300-500 MHz 300-533 MHz 300-600 MHz 300-667 MHz Deep Sleep power 300-500 MHz 300-533 MHz 300-600 MHz 300-667 MHz 1.2-1.6 V 1.2-1.6 V 1.2-1.6 V 1.2-1.6 V 0.1 W 0.1 W 0.1 W 0.1 W Deep Sleep mode is entered by asserting SLEEP# and stopping CLKIN while in Quick Start. Deep Sleep typical power is measured with LongRun power management enabled. Deep Sleep mode is entered by asserting SLEEP# and stopping CLKIN while in Quick Start. Deep Sleep maximum power is specified at CVDD = 1.2V at a 45C junction temperature. 1.2-1.6 V 1.2-1.6 V 1.2-1.6 V 1.2-1.6 V 0.2 W 0.2 W 0.2 W 0.2 W Quick Start mode is entered by asserting STPCLK#. Typical Quick Start power is measured with LongRun power management enabled. 1.2-1.6 V 1.2-1.6 V 1.2-1.6 V 1.2-1.6 V 0.3 W 0.3 W 0.3 W 0.3 W Auto Halt mode is entered by executing a HLT instruction. Typical Auto Halt power is measured with LongRun power management enabled. 1.2-1.6 V 1.2-1.6 V 1.2-1.6 V 1.2-1.6 V 0.7 W 0.7 W 0.7 W 0.7 W Typical operating power is measured while playing MP3 files with Windows Media Player under WindowsTM 98 with LongRun power management enabled. 1.6 V 1.6 V 1.6 V 1.6 V 5.7 W 5.9 W 6.4 W 7.3 W Thermal design power is the maximum average power measured over a 30 second interval, while running commercially available software. TM5400/TM5600 Power Specifications
CVDD Nominal 1
Typical Power 1
Maximum Power 1
Notes
Maximum Deep Sleep power 500 MHz 533 MHz 600 MHz 667 MHz 1. 1.2 V 1.2 V 1.2 V 1.2 V 0.18 W 0.18 W 0.18 W 0.18 W
All power supplies at their nominal values. All power values are the total of core power and I/O power.
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TABLE 31
TM5400/TM5600 Peak Current Specifications
Operating Frequency
500 MHz
Supply CVDD PLLVDD IOVDD25 IOVDD
Maximum Voltage
1.68 V 1.68 V 2.625 V 3.465 V 1.68 V 1.68 V 2.625 V 3.465 V 1.68 V 1.68 V 2.625 V 3.465 V 1.68 V 1.68 V 2.625 V 3.465 V
Peak Current
3.7 A 20 mA 300 mA 300 mA 3.8 A 20 mA 300 mA 300 mA 4.2 A 20 mA 300 mA 300 mA 4.7 A 20 mA 300 mA 300 mA
Notes
All supplies at their maximum values.
533 MHz
CVDD PLLVDD IOVDD25 IOVDD
All supplies at their maximum values.
600 MHz
CVDD PLLVDD IOVDD25 IOVDD
All supplies at their maximum values.
667 MHz
CVDD PLLVDD IOVDD25 IOVDD
All supplies at their maximum values.
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3.4 DC Specifications for I/O Signals
TABLE 32 Symbol
Voh Vol Vih DC Specs for All Signals Except PCI and DDR SDRAM Interfaces
Description
Output high voltage Output low voltage Input high voltage (excluding 2.5V inputs) Input high voltage for 2.5V inputs
Condition
Iout = -1 mA Iout = 1 mA
Minimum
2.4 V 2.0 V 1.7 V
Maximum
0.4 V
Notes
IOVDD IOVDD
The 2.5V input pins are: CLKIN,
IGNNE#, INTR, INIT#, NMI, SMI#, and STPCLK#. The
2.5V input pins are 3.3V tolerant.
Vil Iih Iil Iihz Iilz Cin
Input low voltage Input high leakage current Input low leakage current Hi-Z high leakage current Hi-Z low leakage current Input pin capacitance Vin = IOVDD Vin = 0 V Vin = IOVDD Vin = 0 V
-0.3 V -
0.7 V 10 uA -100 uA 10 uA -10 uA 10 pF Pins loaded at 2.4 pF Pins loaded at 2.4 pF Pins loaded at 2.4 pF Pins loaded at 2.4 pF
TABLE 33
DC Specifications for DDR SDRAM Interface
Symbol
Voh Vol Vih 1 Vil Iih Iil Cin 1.
Description
Output high voltage Output low voltage Input high voltage Input low voltage Input high leakage current Input low leakage current Input pin capacitance
Condition
Iout = -5.0 mA Iout = 7.5 mA
Minimum
1.85 V -
Maximum
0.35 V
C_VREF + 0.18V
-0.3 V Vin = IOVDD25 Vin = 0 V -
IOVDD25 + 0.3V C_VREF - 0.18V
10 uA -100 uA 10 pF
The DDR SDRAM interface inputs are not 3.3V tolerant.
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TABLE 34
DC Specifications for PCI Interface
Symbol
Voh Vol Vih
Description
Output high voltage Output low voltage Input high voltage (excluding
Condition
Iout = -0.5 mA Iout = 1.5 mA
Minimum
0.9 x IOVDD 0.5 x IOVDD 2.0 V -0.5 V -0.5 V
Maximum
0.1 x IOVDD
IOVDD + 0.5V IOVDD + 0.5V
0.3 x IOVDD 0.8 V 10 A - 100 A 10 pF
P_PCLK)
Input high voltage (P_PCLK only) Vil Input low voltage (excluding
P_PCLK)
Input low voltage (P_PCLK only) Iih Iil Cin Input high leakage current Input low leakage current Input pin capacitance Vin = IOVDD Vin = 0 V -
TABLE 35
Thermal Diode Specifications
Symbol
V100 V10 1.
1
1
Description
Forward biased diode drop forcing 100 uA Forward biased diode drop forcing 10 uA
Minimum
-
Typical
0.68 V 0.62 V
Maximum
-
V100 and V10 typical values are measured at 25C while DIODE_CATHODE is biased at 0.7 V.
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3.5 Timing Specifications for I/O Signals
3.5.1 General AC Testing Conditions
Table 36 and Figure 5 specify the general AC test and measurement conditions. These conditions apply unless specified otherwise. TABLE 36
General AC Testing Conditions
Parameter
Vl
Description
3.3V input low drive level 2.5V input low drive level DDR interface input low drive level
Value
0.4 V 0.4 V
C_VREF - 0.35 V
2.4 V 2.0 V
Vh
3.3V input high drive level 2.5V input high drive level DDR interface input high drive level
C_VREF + 0.35 V
1.4 V 1.2 V 1 V/ns
Vm tedge
3.3 V I/O timing specification measurement level 2.5 V I/O timing specification measurement level Input signal edge rate measured between 20% and 80% of drive levels
FIGURE 5
General AC Test and Measurement Conditions
Vh 80% 80%
Vm 20% 20% Vl
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3.5.2
Power On Specifications
Table 37 and Figure 6 document the timing specifications for powering on the TM5400/ TM5600.
TABLE 37
Power On Specifications
Parameter
tvdd_rise
Description
Supply rise time
Minimum
-
Maximum
250 ms
Notes
All supplies must rise from zero to recommended operating levels within the same 250 ms window.
tvdd_pg
PWRGOOD asserted after supplies reach 95% of final value
Supplies stable prior to
0s
-
P_PCI_RST# and RESET# should be active prior to PWRGOOD
asserted.
tvdd_prst
1 ms
-
P_PCI_RST#
deasserted tpclk_prst
P_PCLK stable prior to P_PCI_RST#
deasserted
100 s
-
tclk_prst
CLKIN stable prior to P_PCI_RST#
deasserted
1 ms
-
tprst_rst
P_PCI_RST# deasserted to RESET#
deasserted
0s
-
tpg_rst
PWRGOOD asserted to RESET#, P_PCI_RST#
deasserted
1 ms
-
tpg_low
PWRGOOD inactive pulse width
10
-
CLKINs
60
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FIGURE 6
Power On Timing
P_PCI_RST#
RESET# CVDD, PLLVDD, IOVDD, IOVDD25 PWRGOOD
tpg_rst tvdd_rise tvdd_pg tvdd_prst
tclk_prst
CLKIN
tpclk_prst
P_PCLK
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3.5.3
Input Clocks
Table 38 and Figure 7 document the timing specifications for the input clocks.
TABLE 38
Timing Specifications for Input Clocks
Parameter
fclk (Clock frequency)
Minimum
60.0 MHz 30.0 MHz 15.0 ns 30 ns 7.5 ns 5.2 ns 11 ns 3.375 ns 5.0 ns 11 ns 3.375 ns -
Maximum
66.66 MHz 33.33 MHz 133.33 MHz 16.67 ns 250 ps
Notes
Clocks may be stopped. Not 100% tested. Guaranteed by design/ characterization.
CLKIN P_PCLK S_CLKIN
tcycle (Clock period)
CLKIN P_PCLK S_CLKIN
thigh (Clock high time)
CLKIN P_PCLK S_CLKIN
tlow (Clock low time)
Not 100% tested. Guaranteed by design/ characterization.
CLKIN P_PCLK S_CLKIN
tjitter (Clock jitter)
Not 100% tested. Guaranteed by design/ characterization.
CLKIN
Spread spectrum clock generation (SSCG) is supported under the following conditions: * 66.67 MHz nominal input frequency * +0% / -5.0% maximum upspread / downspread * 30 kHz maximum modulation frequency * 250 ps max. clock jitter
P_PCLK
trise/fall (Clock rise and fall time)
0.4 ns 1.0 ns
500 ps 1.6 ns 4.0 ns
CLKIN P_PCLK
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TABLE 38
Timing Specifications for Input Clocks (Continued)
Parameter
toffset (CLKIN to P_PCLK offset) tpll_lock (PLL relock time)
Minimum
1.5 ns -
Maximum
4.0 ns 20 s
Notes
FIGURE 7
Timing Specifications for Input Clocks
tcycle 2.0 V Vm* CLKIN, P_PCLK, S_CLKIN 0.8 V trise thigh tfall 0.8 V tlow
* Vm = 1.2 V for CLKIN, = 0.4 x IOVDD for P_PCLK = 1.4 V for S_CLKIN
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3.5.4
DDR SDRAM Interface
Table 39 and Table 40, along with Figure 8 and Figure 9 document the timing specifications for the DDR SDRAM interface.
TABLE 39
Timing Specifications for DDR SDRAM Interface
Parameter
fclk tcycle tlow, thigh tjitter Vx tvalid
Description C_CLK frequency C_CLK period C_CLK low time, high time C_CLK jitter
Differential cross pt. voltage Output valid delay:
Minimum
7.5 ns 0.45 bus clks 1.1 V 0.75 bus clks see Table 40 0.76 ns -0.76 ns 0.45 bus clks 0.9 bus clks 0 ns -0.5 ns 1 bus clock 1 bus clock 1 bus clock 1 bus clock 1 bus clock 2 bus clocks 2 bus clocks 4 transfers 128 bus clocks
Maximum
133 MHz 0.55 bus clks 150 ps 1.4 V see Table 40 3.05 ns +0.76 ns 0.55 bus clks 1.1 bus clks
Notes
1 1 1 1 2,3,4
C_DQS CMD signals
tohold tvalid_dqs tohold_dqs tdqs_skew tdqs_low, tdqs_high tdqs_preamble toff Output hold time CMD signals
2,3,4
C_DQ, C_DQMB valid from C_DQS (writes) C_DQ, C_DQMB hold from C_DQS (writes) C_DQS to C_DQ, C_DQMB skew C_DQS input low time, C_DQS input high time C_DQS preamble valid time
Active to float delay C_DQ C_DQS
2 2.5 ns +0.5 ns 16 bus clocks 16 bus clocks 16 bus clocks 16 bus clocks 16 bus clocks 17 bus clocks 17 bus clocks 4 transfers 16k bus clocks 5 5 5 5 5,6 5,7 5,8 9 5
nras_cas ncas_read nread_pchg nwr_pchg nrow_pchg nidmrs nras_ras nburst nrefresh
C_RAS# to C_CAS# latency C_CAS# to read latency
Read precharge delay Write precharge delay Row precharge time Idle cycles after MRS Row cycle time Burst length Refresh rate
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Notes for Table 39: 1. Clock specifications apply to C_CLKA, C_CLKA#, C_CLKB, C_CLKB#. C_CLKA and C_CLKA# are 180 degrees out of phase. C_CLKB and C_CLKB# are 180 degrees out of phase. C_CLKA and C_CLKB are copies of each other. These parameters measured relative to C_CLK/C_CLK# differential cross point voltage. CMD signals are: C_A[12:0], C_BA[1:0], C_CAS#, C_CKE[1:0], C_CS#[3:0],
2. 3. 4. 5. 6. 7. 8.
C_RAS#, C_WE#.
Assumes 80 pF maximum load on each CMD signal and 10 pF maximum load on each of C_DQ[63:0]. These parameters are programmable within the TM5400/TM5600 processor. Row precharge time is the number of bus clocks between the power on precharge and the next time RAS can be asserted. MRS stands for Mode Register Set operation. Row cycle time is the number of bus clocks between refresh and the next time RAS can be asserted for other SDRAM operations. This also is the number of cycles the DDR SDRAM controller waits before starting any SDRAM access after it exits clock off mode. The DDR SDRAM controller always performs burst operations.
9.
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Table 40 provides the DDR SDRAM interface output hold time (tohold) minimum timing and output valid delay (tvalid) maximum timing specifications for each TM5400/TM5600 SKU and LongRun step. The table covers three DDR memory speeds. Refer to TM5400/ TM5600 Development and Manufacturing Guide for additional information on memory configuration. TABLE 40
tohold and tvalid Timing Specifications for DDR SDRAM Interface SKU LongRun Settings MHz 500 500 1.6V 400 300 533 533 1.6V 467 400 300 600 600 1.6V 500 400 300 667 667 1.6V 600 533 400 300 V 1.6 1.4 1.2 1.6 1.5 1.35 1.2 1.6 1.4 1.2 1.6 1.5 1.35 1.2 DDR Interface CLK Divisor / Frequency (MHz) / tohold min (ns) / tvalid max (ns) TM_DDR266CL25 Div Mclk tohold tvalid / 4 125 / 3 133 / 3 100 / 4 133 / 4 117 / 3 133 / 3 100 / 5 120 / 4 125 / 3 100 / 5 133 / 5 120 / 4 133 / 3 100 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TM_DDR250CL25 Div Mclk tohold tvalid / 4 125 / 4 100 / 3 100 / 5 107 / 4 117 / 4 100 / 3 100 / 5 120 / 4 125 / 4 100 / 3 100 / 6 111 / 5 120 / 5 107 / 4 100 / 3 100 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TM_DDR200CL25 Div Mclk tohold tvalid / 5 100 / 4 100 / 3 100 / 6 89 / 5 93 / 4 100 / 3 100 / 6 100 / 5 100 / 4 100 / 3 100 / 7 95 / 6 100 / 6 89 / 4 100 / 3 100 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
1.225 / 4 100
1.225 / 4 100
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FIGURE 8
Timing Specifications for DDR SDRAM Interface - Read Cycle
0 C_CLK# C_CLK C_CKE[1:0]
1
2
3
4
5
6
7
8
9
10
tcycle
nras_cas C_RAS# C_CS#[3:0] C_A[12:0] C_BA[1:0] C_CAS# tdqs_skew C_DQ[63:0] tdqs_preamble IN0 IN1 IN2 IN3 nread_pchg nras_ras VALID tvalid VALID ncas_read
C_DQS[7:0]
tdqs_high
tdqs_low Note: CAS Latency = 2 in this diagram.
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FIGURE 9
Timing Specifications for DDR SDRAM Interface - Write Cycle
0 C_CLK# C_CLK C_CKE[1:0]
1
2
3
4
5
6
7
8
9
10
nras_cas C_RAS# C_CS#[3:0] C_A[12:0] C_BA[1:0] C_CAS# nras_ras VALID VALID
C_WE#
C_DQMB[7:0]
Val0 Val1 Val2 Val3
nwr_pchg C_DQ[63:0]
Out0 Out1 Out2 Out3
tvalid_dqs C_DQS[7:0]
tohold_dqs
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3.5.5
SDR SDRAM Interface
Table 41 and Table 42, along withFigure 10, Figure 11, and Figure 12, document the timing specifications for the SDR SDRAM interface.
TABLE 41
Timing Specifications for SDR SDRAM Interface
Parameter
fclk tsetup tihold tvalid tohold nras_cas ncas_read nread_pchg nwr_pchg nrow_pchg nidmrs nras_ras nburst nrefresh Notes for Table 41: 1. 2. 3. 4.
Description S_CLKIN, S_CLKOUT, S_CLK frequency
Input setup time Input hold time Output valid delay Output hold time
Minimum
1.7 ns 1.9 ns see Table 42 1 bus clock 1 bus clock 1 bus clock 1 bus clock 1 bus clock 2 bus clocks 2 bus clocks 4 transfers 128 bus clocks
Maximum
133 MHz see Table 42 16 bus clocks 16 bus clocks 16 bus clocks 16 bus clocks 16 bus clocks 17 bus clocks 17 bus clocks 4 transfers 16K bus clocks
Notes
1 2, 3 2, 3 2, 4, 5 2, 4, 5, 6 6 6 6 6 6, 7 6, 8 6, 9 10 6
S_RAS# to S_CAS# latency S_CAS# to read latency
Read precharge delay Write precharge delay Row precharge time Idle cycles after MRS Row cycle time Burst length Refresh rate
S_CLK[3:0] are copies of S_CLKOUT.
These parameters measured relative to S_CLKIN rising edge at 1.4 volt level. Input signals are: S_DQ[63:0]. Output signals are: Data= S_DQ[63:0], S_DQMB[7:0] Address= S_A[12:0], S_BA[1:0], S_CAS#, S_RAS#, S_WE# Enables = S_CKE[1:0], S_CS#[3:0] Assumes 50 pF load for output pins. For every 10 pF above a 50 pF load, add 170 pS for the data and enable pins, and 90 pS for the address pins. For every 10 pF below a 50 pF load, subtract 170 pS for the data and enable pins, and 90 pS for the address pins. These parameters are programmable within the TM5400/TM5600 processor. Row precharge time is the number of bus clocks between the power on precharge and the next time RAS can be asserted. MRS stands for Mode Register Set operation. Row cycle time is the number of bus clocks between refresh and the next time RAS can be asserted for other SDRAM operations. This also is the number of cycles the SDR SDRAM controller waits before starting any SDRAM access after it exits clock off mode.
5.
6. 7. 8. 9.
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10. The SDR SDRAM controller always performs burst operations.
FIGURE 10
SDR SDRAM Input Setup/Hold and Output Valid Delay/Hold Timing
S_CLKOUT
tvalid Output Timing: S_DQ[63:0], S_DQMB[7:0], S_A[12:0], S_BA[1:0], S_CAS#, S_RAS#, S_WE#, S_CKE[1:0], S_CS#[3:0]
tohold
tcycle thigh S_CLKIN tlow tsetup Input Timing: S_DQ[63:0]
tihold
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Table 42 provides the SDR SDRAM interface output hold time (tohold) minimum timing and output valid delay (tvalid) maximum timing specifications for each TM5400/TM5600 SKU and LongRun step. The table covers three SDR memory speeds. Refer to TM5400/ TM5600 Development and Manufacturing Guide for additional information on memory configuration. TABLE 42
tohold and tvalid Timing Specifications for SDR SDRAM Interface SKU LongRun Settings MHz 500 500 1.6V 400 300 533 533 1.6V 467 400 300 600 600 1.6V 500 400 300 667 667 1.6V 600 533 400 300 V 1.6 1.4 1.2 1.6 1.5 1.35 1.2 1.6 1.4 1.2 1.6 1.5 1.35 1.2 SDR Interface CLK Divisor / Frequency (MHz) / tohold min (ns) / tvalid max (ns) TM_SDR133CL3 Div Mclk tohold tvalid / 4 125 / 3 133 / 3 100 / 4 133 / 4 117 / 3 133 / 3 100 / 5 120 / 4 125 / 3 100 / 5 133 / 5 120 / 4 133 / 3 100 1.4 2.0 2.4 1.25 1.6 2.0 2.4 1.9 1.5 1.6 2.5 1.6 2.0 1.35 1.65 2.5 4.0 4.0 5.4 3.9 3.7 4.0 5.4 4.5 3.5 4.6 5.4 4.2 4.0 3.4 4.6 5.4 TM_SDR125CL3 Div Mclk tohold tvalid / 4 125 / 4 100 / 3 100 / 5 107 / 4 117 / 4 100 / 3 100 / 5 120 / 4 125 / 4 100 / 3 100 / 6 111 / 5 120 / 5 107 / 4 100 / 3 100 1.4 2.0 2.4 2.2 1.6 2.0 2.4 1.9 1.5 1.6 2.5 1.6 2.0 2.3 1.65 2.5 4.0 4.0 5.4 3.8 3.7 4.0 5.4 4.5 3.5 4.6 5.4 4.2 4.0 4.3 4.6 5.4 TM_SDR100CL3 Div Mclk tohold tvalid / 5 100 / 4 100 / 3 100 / 6 89 / 5 93 / 4 100 / 3 100 / 6 100 / 5 100 / 4 100 / 3 100 / 7 95 / 6 100 / 6 89 / 4 100 / 3 100 1.4 2.0 2.4 2.2 1.6 2.0 2.4 1.9 1.5 1.6 2.5 1.6 2.0 2.3 1.65 2.5 4.0 4.0 5.4 3.8 3.7 4.0 5.4 4.5 3.5 4.6 5.4 4.2 4.0 4.3 4.6 5.4
1.225 / 3 133
1.225 / 3 133
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FIGURE 11
Timing Specifications for SDR SDRAM Interface - Read Cycle 0 1 2 3 4 5 6 7 8 9 10
S_CLKIN
S_CKE[1:0] nras_cas S_RAS# S_CS#[3:0] S_A[12:0] S_BA[1:0] S_CAS# nras_ras VALID VALID ncas_read
S_DQMB[7:0]
VALID0 VALID1 VALID2 VALID3 nread_pchg
S_DQ[63:0]
IN0
IN1
IN2
IN3
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FIGURE 12
Timing Specifications for SDR SDRAM Interface - Write Cycle
0 CLKIN
1
2
3
4
5
6
7
8
9
10
S_CKE[1:0] nras_cas S_RAS# S_CS#[3:0] S_A[12:0] S_BA[1:0] S_CAS# nras_ras VALID VALID
S_WE#
S_DQMB[7:0]
VALID0 VALID1 VALID2 VALID3 nwr_pchg
S_DQ[63:0]
OUT0
OUT1
OUT2
OUT3
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3.5.6
PCI Interface
Table 43 documents the timing specifications for the PCI interface. The TM5400/TM5600 PCI interface is compliant with revision 2.1 of the PCI Local Bus Specification. Refer to the PCI specification for additional information.
TABLE 43
Timing Specifications for PCI Interface
Parameter
fclk tsetup
Description P_PCLK frequency
Input setup time
Minimum
30.0 MHz 12 ns 7 ns 0 ns 2 ns 2 ns -
Maximum
33.33 MHz 12 ns 11 ns 28 ns 40 ns
Notes
P_REQ#[5:0]
All other inputs tihold tvalid Input hold time Output valid delay
1, 2 1, 2 1, 3
P_GNT#[5:0]
All other outputs toff trst_off Notes for Table 43: 1. 2. Active to float delay
P_PCI_RST# asserted to output float delay
These parameters measured relative to P_PCLK rising edge at 0.4*IOVDD level. Input signals are: P_AD[31:0], P_C/BE#[3:0], P_CLKRUN#, P_DEVSEL#, P_FRAME#, P_HOLD#, P_IRDY#, P_LOCK#, P_PAR, P_PCI_RST#, P_PERR#, P_REQ#[5:0], P_SERR#, P_STOP#, P_TRDY#. Output signals are: P_AD[31:0], P_C/BE#[3:0], P_CLKRUN#, P_DEVSEL#, P_FRAME#, P_GNT#[5:0], P_HLDA#, P_IRDY#, P_LOCK#, P_PAR, P_PERR#, P_STOP#, P_TRDY#.
3.
3.5.7
Southbridge Sidebands and Power Management Interface
IGNNE#, INIT#, INTR, NMI, PWRGOOD, SLEEP#, SMI# and STPCLK# are asynchronous input signals. Therefore, these inputs are not required to meet any setup and hold specifications.
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3.5.8
Debug Interface
Table 44 and Figure 13 document the timing specifications for the debug serial interface.
TABLE 44
Timing Specifications for Debug Interface
Parameter
fclk tcycle thigh tlow trise tfall tstop_sta tsta_setup tsta_hold tstop_hold tsetup tihold tvalid tohold Notes for Table 44: 1. 2. 3. 4. 5. 6.
Description S_SCLK frequency S_SCLK period S_SCLK high time S_SCLK low time S_SCLK, S_SDATA rise time S_SCLK, S_SDATA fall time
Bus free to new transaction Start condition setup time Start condition hold time Stop condition setup time
Minimum
0 2.5 s 600 ns 1.3 s 1.3 s 600 ns 600 ns 600 ns 100 ns 0 ns 250 ns
Maximum
400 KHz 1 s 300 ns 350 ns -
Notes
1 1 1 2 2 3, 4 3, 5 4, 6 4 5 5 5
S_SDATA input setup time S_SDATA input hold time S_SDATA output valid delay S_SDATA output hold time
Not 100% tested. Guaranteed by design/characterization. Rise and fall times are measured from 20% to 80%. Start condition occurs when S_SDATA transitions from high to low while S_SCLK is high. These conditions measured relative to S_SCLK rising edge at 1.5 volt level. Assumed loading is 400 pF. These conditions measured relative to S_SCLK falling edge at 1.5 volt level. Assumed loading is 400 pF. Stop condition occurs when S_SDATA transitions from low to high while S_SCLK is high.
FIGURE 13
Timing Specifications for Debug Interface tcycle
S_SCLK tsta_hold S_SDATA tsta_setup START tihold tsetup IN tvalid tohold OUT
tstop_sta tstop_hold STOP
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3.5.9
Code Morphing Software Boot ROM Interface
Table 45 and Figure 14 document the timing specifications for the Code Morphing software boot ROM serial interface.
TABLE 45
Code Morphing Software Boot ROM Interface Timing Specifications
Parameter
fclk tcycle thigh tlow tsetup1 tihold1 tcs_high tsetup2 tihold2 tvalid tohold toff Notes for Table 45: 1. 2.
Description SROM_SCLK frequency SROM_SCLK period SROM_SCLK high time SROM_SCLK low time SROM_CS# input setup time SROM_CS# input hold time SROM_CS# high time SROM_SIN input setup time SROM_SIN input hold time SROM_SOUT output valid
delay
Minimum
90 ns 40 ns 40 ns 350 ns 350 ns 100 ns 20 ns 0 ns 35 ns -
Maximum
11 MHz 85 ns 100 ns
Notes
1 2 1 1 2 2
SROM_SOUT output hold time SROM_SOUT active to float
delay
These conditions measured relative to SROM_SCLK rising edge at 1.4 volt level. These conditions measured relative to SROM_SCLK falling edge at 1.4 volt level.
FIGURE 14
Code Morphing Software Boot ROM Interface Timing Specifications tcycle SROM_SCLK tsetup1 SROM_CS# tsetup2 SROM_SIN VALID tihold2 SROM_SOUT VALID tvalid VALID tohold toff tihold1
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3.5.10 Configuration ROM Interface
Table 46 and Figure 15 document the timing specifications for the configuration ROM interface. TABLE 46
Timing Specifications for Configuration ROM Interface
Parameter
fclk tcycle thigh tlow tprst_clk tsetup tihold tvalid tohold Notes for Table 46: 1. 2.
Description CFG_SCLK frequency CFG_SCLK clock period CFG_SCLK high time CFG_SCLK low time P_PCI_RST# to CFG_SCLK
active high
Minimum
0.5 s 250 ns 250 ns 100 ns 600 s 0s 100 ns
Maximum
2 MHz 2 s 900 s -
Notes
1
CFG_SDATA input setup time CFG_SDATA input hold time CFG_SDATA output valid
delay
2 2 2 2
CFG_SDATA output hold time
CFG_SCLK period is CLKIN period x 72. For 66 MHz CLKIN, CFG_SCLK period is 1.08 s.
These parameters measured relative to CFG_SCLK rising edge at 1.4 volt level.
FIGURE 15
Timing Specifications for Configuration ROM Interface tprst_clk
P_PCI_RST#
tcycle
CFG_SCLK
tvalid
CFG_SDATA
tohold
Address Out
tsetup
Address Out
tihold
Data In Data In
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3.5.11 JTAG Interface
Table 47 and Figure 16 document the timing specifications for the JTAG interface. TRST# is an asynchronous pin. Therefore there is no setup or hold time specified for TRST# in Table 47. TABLE 47
Timing Specifications for JTAG Interface
Parameter
fclk tcycle tlow thigh trise tfall treset tsetup1 thold1 ton1 toff1 tsetup2 thold2 tvalid2 toff2 Notes for Table 47: 1. 2.
Description TCK frequency TCK clock period TCK low time TCK high time TCK rise time TCK fall time TRST# pulse width TDI, TMS input setup time TDI, TMS input hold time TDO float to active delay TDO active to float delay
Non-test inputs setup time Non-test inputs hold time Non-test outputs valid delay Non-test outputs active to float delay
Minimum
20 ns 8 ns 8 ns 200 ns 10 ns 10 ns 5 ns 10 ns -
Maximum
50 MHz 2 ns 2 ns 10 ns 10 ns 10 ns 10 ns 20 ns
Notes
1 1 2 2 1 1 2 2
These parameters measured relative to TCK rising edge at 1.4 volt level. These parameters measured relative to TCK falling edge at 1.4 volt level.
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FIGURE 16
Timing Specifications for JTAG Interface
tcycle TCK tsetup1 TDI, TMS tsetup2 Non-test inputs
Valid Valid
thold1
thold2 ton1 toff1
Valid
TDO tvalid2 Non-test outputs
toff2
Valid
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Chapter 4
Mechanical Specifications
4.1 Thermal Specifications
The maximum junction temperature for the TM5400/TM5600 is 85C. The junction-topackage top (exposed silicon die) thermal resistance (jp) is 0.075C/W, and the junctionto-PCB thermal resistance (jb) is 3.3C/W. For detailed information on processor thermal characteristics and thermal solution design, please refer to the TM5400/TM5600 Thermal Design Guide.
4.1.1
Thermal Diode
TM5400/TM5600 Version 1.2
The TM5400/TM5600 v1.2 on-die thermal diode, when used in conjunction with a Maxim MAX1617MEE (standard part) temperature sensor, will provide a temperature accuracy of +/- 3C from 0-to-100C. The system BIOS will provide an offset of 1C for temperature correction when it recognizes a TM5400/TM5600 version 1.2 device.
TM5400/TM5600 Versions 1.0 and 1.1
The TM5400/TM5600 v1.0 and v1.1on-die thermal diodes, when used in conjunction with a Maxim MAX1617TMEE (Transmeta-specific) temperature sensor, will provide a temperature accuracy of +/- 3C from 0-to-100C. The Transmeta-specific MAX1617TMEE must be used for TM5400/TM5600 version 1.0 and 1.1 devices - the standard MAX1617MEE will not provide any guaranteed level of accuracy. The system BIOS will provide an offset of 6C for temperature correction when it recognizes TM5400/TM5600 version 1.0 and 1.1 devices.
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4.2 Package Dimensions
The TM5400/TM5600 processor is packaged in a 474-pin ceramic ball-grid array. The dimensions for this package are shown in the drawings on the following pages. For more information on the TM5400/TM5600 package, see the Crusoe Processor Model TM5400/ TM5600 Package Specifications and Manufacturing Guide.
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4.3 Package Marking
Figure 17 shows the location of the TM5400/TM5600 package markings. The fields shown are described in detail in Table 48. FIGURE 17
Package Marking Locations - Top View
Transmeta
TM5x00-MN TTTTTTTTTT VV
+ + LLLLLLLLLL 1111111111 8888888888
Canada YYWWSS
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TABLE 48
Package Marking Descriptions
Field TM5x00-MN
Description
Part name and revision number
TM5400
or
Part name
TM5600 M N 1111111111 8888888888 TTTTTTTTTT VV
Major revision number Minor revision number
Level 01 lot number - associated with the speed sort lot. Level 08 lot number - associated with the assembly lot. Transmeta manufacturing part number - identifies product SKU. Quality level indicator - ES for engineering sample, MS for mechanical sample; if left blank, the quality level is pre-production (PP) or mass (MP). Country of origin - currently all TM5400/TM5600 parts are assembled in Canada. Date code/modification code - year (YY) and workweek (WW) the part was assembled; SS is a product modification code for modifications not indicated by major and minor revision numbers. Substrate part number - assigned by the substrate manufacturer. Balling rework status - each + indicates one BGA balling rework cycle.
Canada YYWWSS
LLLLLLLLLL +
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